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US4742452A
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Computer system including address driven program interrupt system
Assignee: Mitsubishi Electric Corp
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Filing: 1986-09-09
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Granted: 1988-05-03
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Expires: 2006-09-09
Abstract
Abstract A computer system, such as a microprocessor-based computer system, which includes a program supervisory device for interrupting operations of the central processing unit of the computer system at any designated address, even in a case where the central processing unit has an instruction advance reading function. The interrupt address is stored in a register. A comparator outputs a coincidence signal when the interrupt address coincides with the current address supplied to the system memory. At that time, a multiplexer disposed in the system data bus disconnects the central processing unit from the memory and reconnects it via the system data bus to a register in which there has been prestored an interrupt or other instruction.
Inventors
- 👤 Masayuki Hirokawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 14:04
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/46; G06F9/48; G06F9/4806; G06F9/4812; G06F11/00; G06F11/22; G06F11/25
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
304 words
A computer system including a program supervisory device, said system comprising: a central processing unit; at least two instruction code sources for selectively transmitting instruction codes to said central processing unit; a system data bus coupled to said central processing unit; a system address bus coupled to said central processing unit; said first instruction code source comprising means for storing at least one predetermined instruction code; said second instruction code source being coupled to said system address bus and comprising a memory for storing therein a plurality of instruction codes at individual addresses thereof, and for supplying instruction codes to said central processing unit over said system data bus in response to addresses supplied from said central processing unit on said system address bus; and means for selectively coupling said central processing unit, via said system data bus, to either (1) said first instruction code source or (2) said second instruction code source, said coupling means including means operatively coupled to said system address bus and responsive only to the addresses carried by said system address bus for generating a signal in response to the appearance on said system address bus of at least one preselected address generated by said central processing unit, and means for selecting a respective instruction code source and for coupling said selected instruction code source to said central processing unit via said system data bus in response to said signal; said selecting means comprising a multiplexer coupled to said system data bus and receiving as multiplexer inputs the outputs of said first and second instruction code sources; and said signal generating means comprising comparator means for comparing a predetermined interrupt address with addresses placed on said system address bus by said central processing unit, an output of said comparator being applied as a selection control input to said multiplexer.
Claim 2
Dependent Claim
304 words
A computer system including a program supervisory device, said system comprising: a central processing unit; at least two instruction code sources for selectively transmitting instruction codes to said central processing unit; a system data bus coupled to said central processing unit; a system address bus coupled to said central processing unit; said first instruction code source comprising means for storing at least one predetermined instruction code; said second instruction code source being coupled to said system address bus and comprising a memory for storing therein a plurality of instruction codes at individual addresses thereof, and for supplying instruction codes to said central processing unit over said system data bus in response to addresses supplied from said central processing unit on said system address bus; and means for selectively coupling said central processing unit, via said system data bus, to either (1) said first instruction code source or (2) said second instruction code source, said coupling means including means operatively coupled to said system address bus and responsive only to the addresses carried by said system address bus for generating a signal in response to the appearance on said system address bus of at least one preselected address generated by said central processing unit, and means for selecting a respective instruction code source and for coupling said selected instruction code source to said central processing unit via said system data bus in response to said signal; said selecting means comprising a multiplexer coupled to said system data bus and receiving as multiplexer inputs the outputs of said first and second instruction code sources; and said signal generating means comprising comparator means for comparing a predetermined interrupt address with addresses placed on said system address bus by said central processing unit, an output of said comparator being applied as a selection control input to said multiplexer.
Claim 3
Dependent Claim
16 words
The computer system of claim 1, further comprising register means for storing said predetermined interrupt address.
Claim 4
Dependent Claim
21 words
The computer system of claim 2, wherein an input port of said register means is coupled to said system data bus.
Claim 5
Dependent Claim
89 words
The computer system of claim 2, further comprising address coincidence detector means having an input port coupled to said system address bus and an output coupled to an interrupt input of said central processing unit, for comparing addresses put on said system address bus by said central processing unit with at least one predetermined address stored in said coincidence detector means, and for generating an interrupt signal on said output in response to the detection of coincidence between the address on said system address bus and said stored address.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-05-03 | 1991-11-02 | 1992-05-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-05-03 | 1995-11-02 | 1996-05-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-05-03 | 1999-11-02 | 2000-05-03 | $7700.00 | Window Closed / Lapsed |