Patent US4733393A successfully refreshed from Google Patents.
US4733393A
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Test method and apparatus for cellular array processor chip
Assignee: ITT Inc
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Filing: 1985-12-12
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Granted: 1988-03-22
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Expires: 2005-12-12
Abstract
Abstract A cellular array processor chip includes a common bus communicating with the individual cells thereof. The common bus can be monitored during chip testing to detect the presence, or absence, of a defective cell. Each cell can be inactivated with respect to the common bus. During testing if the presence of a defective cell is determined to exist each cell is individually tested until a defective cell is located. That cell is inactivated and the chip testing is resumed until all defective cells are located and inactivated.
Inventors
- 👤 Steven G. Morton
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 21:38
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/22; G06F11/2205; G06F11/2236; G06F1/00; G06F1/22; G06F11/006; G06F15/00; G06F15/76; G06F15/78; G06F15/7896; G06F15/80; G06F15/8007; G06J; G06J1/00; G11; G11C; G11C29/00; G11C29/006; G06F11/07; G06F11/08; G06F11/10
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
73 words
A cellular array processor chip comprising: a plurality of processor cells; means associated with said chip, for simultaneously monitoring a plurality of said processor cells during chip testing, said means including a common bus, said common bus communicating with all of said plurality of processor cells whereby the signal on said common bus is indicative of the presence or absence of a defective cell among said plurality of processor cells on said chip.
Claim 2
Dependent Claim
73 words
A cellular array processor chip comprising: a plurality of processor cells; means associated with said chip, for simultaneously monitoring a plurality of said processor cells during chip testing, said means including a common bus, said common bus communicating with all of said plurality of processor cells whereby the signal on said common bus is indicative of the presence or absence of a defective cell among said plurality of processor cells on said chip.
Claim 3
Dependent Claim
25 words
The cellular array processor chip as claimed in claim 1 further comprising: means for initializing all of said plurality of cells to the same state.
Claim 4
Dependent Claim
57 words
The cellular array processor chip as claimed in claim 2 further comprising: means responsive to said initializing of all of said plurality of cells to the same state and an indication of a defective cell on said common bus for removing the signal from a defective cell from said common bus whereby the chip testing can resume.
Claim 5
Dependent Claim
30 words
The cellular array processor chip as claimed in claim 1 further comprising: means, responsive to an external instruction, for initializing all of said plurality of cells to be simultaneously tested.
Claim 6
Dependent Claim
71 words
The cellular array processor chip as claimed in claim 4 wherein said initializing means includes: a programmable logic device, said device being responsive to said external instruction; and a plurality of cell enabling devices, each being associated with one of said cells, said enabling devices being responsive to a signal from said programmable logic device whereby a plurality of cells can be simultaneously initialized and defective cells can be turned off.
Claim 7
Dependent Claim
19 words
The cellular processor chip as claimed in claim 5 wherein each said cell enabling device includes a pull-up transistor.
Claim 8
Independent Claim
60 words
A method of testing a cellular array processor chip having a plurality of processor cells, said method comprising the steps of: initializing all of said plurality of said cells, said cells being connected to a common bus; and monitoring said common bus whereby if any of said plurality of cells is defective the signal on said common bus indicates same.
Claim 9
Independent Claim
60 words
A method of testing a cellular array processor chip having a plurality of processor cells, said method comprising the steps of: initializing all of said plurality of said cells, said cells being connected to a common bus; and monitoring said common bus whereby if any of said plurality of cells is defective the signal on said common bus indicates same.
Claim 10
Dependent Claim
46 words
Method as claimed in claim 7 further comprising the steps of: testing, in response to said signal of a defective cell, each of said plurality of cells; turning off the first found defective cell; and reinitializing all of said plurality of cells except said defective cell.
Claim 11
Dependent Claim
31 words
Method as claimed in claim 8, further comprising the step of: storing an indication of the location of said defective cell whereby said defective cell is removered from all further testing.
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-03-22 | 1991-09-21 | 1992-03-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-03-22 | 1995-09-21 | 1996-03-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-03-22 | 1999-09-21 | 2000-03-22 | $7700.00 | Window Closed / Lapsed |