Patent US4732871A successfully refreshed from Google Patents.
US4732871A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Process for producing undercut dummy gate mask profiles for MESFETs
Assignee: International Business Machines Corp
•
Filing: 1987-03-30
•
Granted: 1988-03-22
•
Expires: 2007-03-30
Abstract
Abstract Process for producing temperature-stable undercut profiles for use in semiconductor fabrication. The process is based on the phenomenon of high etch-rate selectivity between RF- and LF- PECVD-grown silicon nitride films (12G and 13G, respectively) that are deposited on top of each other. By choosing proper film and process parameters, these PECVD nitride structures can be made stress-free: the tensile stress of the RF film (12G) compensates the compressive stress of the LF film (13G). Also disclosed is an application of a T-shaped structure (15), produced with the new process, in a method for fabricating fully self-aligned "dummy" gate sub-micron MESFETs.
Inventors
- 👤 Peter L. Buchmann
- 👤 Volker Graf
- 👤 Peter D. Hoh
- 👤 Theodor O. Mohr
- 👤 Peter Vettiger
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 12:25
CPC Classifications
H; H10; H10P; H10P14/00; H10P14/60; H10P14/63; H10P14/6326; H10P14/6328; H10P14/6334; H10P14/6336; H10D; H10D30/00; H10D30/01; H10D30/061; H10D30/0612; H10D30/0614; H10D64/00; H10D64/01; H10D64/012; H10D64/0124; H10D64/0125; H10D64/017; H10P14/66; H10P14/668; H10P14/6681; H10P14/6682; H10P14/68; H10P14/69; H10P14/692; H10P14/6921; H10P14/6922; H10P14/6927; H10P14/694; H10P14/6943; H10P14/69433; H10P50/00; H10P50/20; H10P50/28; H10P50/282; H10P50/283; H10P76/00; H10P76/40; H10P76/408; H10P76/4085
Claims Analysis
Total Claims: 30
Claim 1
Independent Claim
143 words
A process for fabricating undercut mask profiles for use in semiconductor device manufacturing comprising the steps of: depositing a first layer of dielectric material on the surface of a substrate in a plasma enhanced chemical vapor deposition reactor at a first plasma excitation frequency to impart a given etch rate to said first layer, depositing a second layer of dielectric material on said first layer at a second plasma excitation frequency to impart an etch rate lower than said given etch rate to said second layer, patterning said first and second layers such that at least one vertical edge of each of said layers is exposed, and etching said first and second layers at said at least one vertical edge to remove portions of said first layer at a rate higher than the rate at which portions of said second layer are removed.
Claim 2
Dependent Claim
143 words
A process for fabricating undercut mask profiles for use in semiconductor device manufacturing comprising the steps of: depositing a first layer of dielectric material on the surface of a substrate in a plasma enhanced chemical vapor deposition reactor at a first plasma excitation frequency to impart a given etch rate to said first layer, depositing a second layer of dielectric material on said first layer at a second plasma excitation frequency to impart an etch rate lower than said given etch rate to said second layer, patterning said first and second layers such that at least one vertical edge of each of said layers is exposed, and etching said first and second layers at said at least one vertical edge to remove portions of said first layer at a rate higher than the rate at which portions of said second layer are removed.
Claim 3
Dependent Claim
17 words
A process according to claim 1 wherein said first and second layers of dielectric material are nitrides.
Claim 4
Dependent Claim
15 words
A process according to claim 1 wherein said substrate is made of a semiconductor material.
Claim 5
Dependent Claim
20 words
A process according to claim 1 wherein said first and second layers of dielectric material are made of silicon nitride.
Claim 6
Dependent Claim
20 words
A process according to claim 1 wherein said first and second layers of dielectric material are made of boron nitride.
Claim 7
Dependent Claim
29 words
A process according to claim 1 wherein said first and second layers of dielectric material are made of nitrides selected from the group consisting of silicon and boron nitride.
Claim 8
Dependent Claim
30 words
A process according to claim 1 wherein said first plasma excitation frequency is in a range of 1 to 50 MHz and said second excitation frequency is below 100 kHz.
Claim 9
Dependent Claim
13 words
A process according to claim 1 wherein said substrate is made of silicon.
Claim 10
Dependent Claim
13 words
A process according to claim 1 wherein said substrate is made of gallium-arsenide.
Claim 11
Dependent Claim
87 words
A process according to claim 1 wherein the step of depositing a first layer of dielectric material includes the steps of: introducing into said reactor a gas comprising NH 3 :N 2 :SiH 4 in the proportions 18:3:55, respectively, at a pressure of about 0.1 Pa, heating said substrate to a temperature of 300° C., and exciting said gas at a frequency of 13 MHz and a power of 75 watts to deposit a layer of silicon nitride at a rate of 20-30 nm/min. on said substrate.
Claim 12
Dependent Claim
86 words
A process according to claim 1 wherein the step of depositing a second layer of dielectric material includes the steps of: introducing into said reactor a gas comprising N 2 :SiH 4 in the proportions 4:50, respectively, at a pressure of about 0.1 Pa, heating said substrate to a temperature of 300° C., and exciting said gas at a frequency of 50 kHz and a power of 75 watts to deposit a layer of silicon nitride at a rate of 20-30 nm/min. on said first layer.
Claim 13
Dependent Claim
49 words
A process according to claim 1 wherein the step of patterning said first and second layers includes the steps of: forming a photoresist mask on the surface of said second layer, and etching said first and second layers to remove portions of said layers not covered by said mask.
Claim 14
Dependent Claim
57 words
A process according to claim 1 wherein the step of etching said first and second layers includes the step of exposing said at least one vertical edge of said first and second layers to a wet chemical etch so that portions of said first layer are removed at a higher rate than portions of said second layer.
Claim 15
Dependent Claim
57 words
A process according to claim 1 wherein the step of etching said first and second layers includes the steps of exposing said at least one vertical edge of said first and second layers to a dry plasma etch so that portions of said first layer are removed at a higher rate than portions of said second layer.
Claim 16
Dependent Claim
178 words
A process for fabricating undercut mask profiles for use in the fabricating of a fully self-aligned field effect transistor which includes a gate and source and drain elements formed in a semiconductor substrate having a current channel disposed therebetween comprising the steps of: depositing a first layer of nitride on the surface of said substrate in a plasma enhanced chemical vapor deposition reactor at a first plasma excitation frequency to impart a given etch rate to said first layer, depositing a second layer of nitride on said first layer at a second plasma excitation frequency to impart an etch rate lower than said given etch rate to said second layer, patterning said first and second layers such that at least one vertical edge of each of said layers is exposed, and etching said first and second layers at said at least one vertical edge to remove portions of said first layer at a rate higher than the rate at which portions of said second layer are removed and provide an undercut mask structure having a T-shaped cross section.
Claim 17
Dependent Claim
178 words
A process for fabricating undercut mask profiles for use in the fabricating of a fully self-aligned field effect transistor which includes a gate and source and drain elements formed in a semiconductor substrate having a current channel disposed therebetween comprising the steps of: depositing a first layer of nitride on the surface of said substrate in a plasma enhanced chemical vapor deposition reactor at a first plasma excitation frequency to impart a given etch rate to said first layer, depositing a second layer of nitride on said first layer at a second plasma excitation frequency to impart an etch rate lower than said given etch rate to said second layer, patterning said first and second layers such that at least one vertical edge of each of said layers is exposed, and etching said first and second layers at said at least one vertical edge to remove portions of said first layer at a rate higher than the rate at which portions of said second layer are removed and provide an undercut mask structure having a T-shaped cross section.
Claim 18
Dependent Claim
118 words
A process according to claim 15 further including the steps of: ion implanting to form source and drain regions within said semiconductor substrate at both ends of said current channel using said T-shaped structure as a mask, depositing ohmic contact metallization onto said source and drain regions, applying and planarizing a reflowable dielectric to embed said T-shaped structure, removing the portion of said dielectric that covers the top of said T-shaped structure, removing said T-shaped structure to expose the surface region over said current channel where said gate electrode is to be formed, depositing a gate metallization, and removing the remaining portion of said dielectric together with those sections of said gate metallization deposited on top of it.
Claim 19
Dependent Claim
19 words
A process according to claim 15 wherein said first and second layers of nitride are made of silicon nitride.
Claim 20
Dependent Claim
19 words
A process according to claim 15 wherein said first and second layers of nitride are made of boron nitride.
Claim 21
Dependent Claim
26 words
A process according to claim 15 wherein said first and second layers of nitrides are nitrides selected from the group consisting of silicon and boron nitride.
Claim 22
Dependent Claim
30 words
A process according to claim 15 wherein said first plasma excitation frequency is in a range of 1 to 50 MHz and said second excitation frequency is below 100 kHz.
Claim 23
Dependent Claim
11 words
A process according to claim 15 wherein said semiconductor is silicon.
Claim 24
Dependent Claim
11 words
A process according to claim 15 wherein said semiconductor is galliumarsenide.
Claim 25
Dependent Claim
86 words
A process according to claim 15 wherein the step of depositing a first layer of nitride includes the steps of: introducing into said reactor a gas comprising NH 3 :N 2 :SiH 4 in the proportions 18:3:55, respectively, at a pressure of about 0.1 Pa, heating said substrate to a temperature of 300° C., and exciting said gas at a frequency of 13 MHz and a power of 75 watts to deposit a layer of silicon nitride at a rate of 20-30 nm/min. on said substrate.
Claim 26
Dependent Claim
85 words
A process according to claim 15 wherein the step of depositing a second layer of nitride includes the steps of: introducing into said reactor a gas comprising N 2 :SiH 4 in the proportions 4:50, respectively, at a pressure of about 0.1 Pa, heating said substrate to a temperature of 300° C., and exciting said gas at a frequency of 50 kHz and a power of 75 watts to deposit a layer of silicon nitride at a rate of 20-30 nm/min. on said first layer.
Claim 27
Dependent Claim
49 words
A process according to claim 15 wherein the step of patterning said first and second layers includes the steps of: forming a photoresist mask on the surface of said second layer, and etching said first and second layers to remove portions of said layers not covered by said mask.
Claim 28
Dependent Claim
57 words
A process according to claim 15 wherein the step of etching said first and second layers includes the step of exposing said at least one vertical edge of said first and second layers to a wet chemical etch so that portions of said first layer are removed at a higher rate than portions of said second layer.
Claim 29
Dependent Claim
57 words
A process according to claim 15 wherein the step of etching said first and second layers includes the steps of exposing said at least one vertical edge of said first and second layers to a dry plasma etch so that portions of said first layer are removed at a higher rate than portions of said second layer.
Claim 30
Dependent Claim
20 words
A process according to claim 16 whrein said gate forms a Schottky barrier at an interface with said current channel.
References Cited (Backward Citations)
US3639186A
Cited
US4503599A
Cited
US4561169A
Cited
US4642879A
Cited
US4519127A
Cited
US4532004A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-03-22 | 1991-09-21 | 1992-03-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-03-22 | 1995-09-21 | 1996-03-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-03-22 | 1999-09-21 | 2000-03-22 | $7700.00 | Window Closed / Lapsed |