Patent US2965460A successfully refreshed from Google Patents.
Patent US4729002A successfully refreshed from Google Patents.
US4729002A
Expired / Lapsed
US
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Self-aligned sidewall gate IGFET
Assignee: Semiconductor Energy Laboratory Co Ltd
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Filing: 1985-08-26
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Granted: 1988-03-01
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Expires: 2005-08-26
Abstract
Abstract A semiconductor device which is provided with a surface channel type or bulk channel type MIS FET. The MIS FET comprises at least a semiconductor substrate of a first conductivity type, a layer member formed in a predetermined pattern on the major surface of the substrate and having an insulating side surface; an insulating layer formed on the major surface of the substrate to extend from the insulating side surface in a direction opposite from the layer member; a conductive layer formed on the major surface of the insulating layer in contact with the insulating side surface of the layer member; and a first semiconductor region of a second conductivity type formed in the semiconductor substrate having a marginal edge corresponding to that of the conductive layer. The first semiconductor region serves as either one of source and drain regions; that region of the semiconductor substrate underlying the conductive layer serves as a channel forming region; that region of the conductive layer facing the channel forming region serves as a gate electrode; and that region of the insulating layer underlying the gate electrode serves as a gate insulating layer. The MIS FET can easily be combined with another MIS FET, a resistance element or capacitance element which is formed through utilization of the layer member of the former.
Inventors
- 👤 Shunpei Yamazaki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 07:57
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0221; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/05; H10D1/00; H10D1/40; H10D1/47; H10D1/60; H10D1/68; H10D30/60; H10D64/00; H10D64/01; H10D64/011; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01326; H10D64/0133; H10D64/20; H10D64/23; H10D64/251; H10D64/258; H10D64/259; H10D64/27; H10D64/311; H10D64/411; H10D64/511; H10D64/517; H10D64/518; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0147; H10D84/02; H10D84/03; H10D84/038; Y; Y10; Y10S; Y10S148/00; Y10S148/111; Y10S148/141; Y10S257/00; Y10S257/90
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
358 words
A semiconductor device comprising: a semiconductor substrate of a first conductivity type; a layer member formed in a predetermined pattern on the major surface of the semiconductor substrate and having a first insulating side surface; a first insulating layer formed on the major surface of the semiconductor substrate and extending from the first insulating side surface of the layer member; a first conductive layer formed on the first insulating layer in contact with the first insulating side surface of the layer member, said first conductive layer having a marginal edge extending upwardly from said first insulating layer, and said first conductive layer having a length which extends substantially parallel to said first insulating side surface and a width which extends in a direction substantially perpendicular to said first insulating side surface, said width extending only from said marginal edge to said first insulating side surface; a first semiconductor region of a second conductivity type reverse from the first conductivity type, formed in the semiconductor substrate from the side of its major surface and having a marginal edge extending downwardly from the major surface such that the latter marginal edge is substantially aligned with the marginal edge of the first conductive layer, the first semiconductor region extending from its marginal edge away from the first conductive layer; a second semiconductor region of the second conductivity type formed in the semiconductor substrate from the side of its major surface to underlie the layer member in contact therewith, the second semiconductor region having a marginal edge extending downwardly from the major surface such that the marginal edge of said second semiconductor region is substantially aligned with the first insulating side surface of the layer member, the second semiconductor region extending from its marginal edge away from the first conductive layer; wherein a first insulated gate field effect transistor is constituted using the first conductive layer as its gate electrode, that region of the first insulating layer underlying the gate electrode as its gate insulating layer, the first semiconductor region as either one of its source and drain regions, the second semiconductor region as the other of its source and drain regions.
Claim 2
Dependent Claim
358 words
A semiconductor device comprising: a semiconductor substrate of a first conductivity type; a layer member formed in a predetermined pattern on the major surface of the semiconductor substrate and having a first insulating side surface; a first insulating layer formed on the major surface of the semiconductor substrate and extending from the first insulating side surface of the layer member; a first conductive layer formed on the first insulating layer in contact with the first insulating side surface of the layer member, said first conductive layer having a marginal edge extending upwardly from said first insulating layer, and said first conductive layer having a length which extends substantially parallel to said first insulating side surface and a width which extends in a direction substantially perpendicular to said first insulating side surface, said width extending only from said marginal edge to said first insulating side surface; a first semiconductor region of a second conductivity type reverse from the first conductivity type, formed in the semiconductor substrate from the side of its major surface and having a marginal edge extending downwardly from the major surface such that the latter marginal edge is substantially aligned with the marginal edge of the first conductive layer, the first semiconductor region extending from its marginal edge away from the first conductive layer; a second semiconductor region of the second conductivity type formed in the semiconductor substrate from the side of its major surface to underlie the layer member in contact therewith, the second semiconductor region having a marginal edge extending downwardly from the major surface such that the marginal edge of said second semiconductor region is substantially aligned with the first insulating side surface of the layer member, the second semiconductor region extending from its marginal edge away from the first conductive layer; wherein a first insulated gate field effect transistor is constituted using the first conductive layer as its gate electrode, that region of the first insulating layer underlying the gate electrode as its gate insulating layer, the first semiconductor region as either one of its source and drain regions, the second semiconductor region as the other of its source and drain regions.
Claim 3
Dependent Claim
87 words
A semiconductor device according to claim 1 wherein the layer member includes a second conductive layer extending on the second semiconductor region, a resistance layer formed on the second conductive layer and a second insulating layer extending on the first side surfaces of the second conductive layer and the resistance layer, the resistance layer constituting a resistance element coupled with the second semiconductor region through the second conductive layer, and the surface of the second insulating layer forming the first insulating side surface of the layer member.
Claim 4
Dependent Claim
55 words
A semiconductor device according to claim 1 wherein the layer member includes a second conductive layer extending on the second semiconductor region and a second insulating layer extending on the first side surface of the second conductive layer, the surface of the second insulating layer forming the first insulating side surface of the layer member.
Claim 5
Dependent Claim
54 words
A semiconductor device according to claim 1 wherein the layer member includes a resistance layer extending on the second semiconductor region and a second insulating layer extending on the first side surface of the first resistance layer, the surface of the second insulating layer forming the first insulating side surface of the layer member.
Claim 6
Dependent Claim
245 words
A semiconductor device according to claim 1 wherein the layer member has a second insulating side surface, and which further comprises a second insulating layer formed on the major surface of the semiconductor substrate extending from the second insulating side surface of the layer member; a second conductive layer formed on the second insulating layer in contact with the second insulating side surface of the layer member, and second conductive layer having a marginal edge extending upwardly from said second insulating layer and said second conductie layer having a length which extends substantially parallel to said second insulating side surface and a width which extends in a direction substantially perpendicular to said second insulating side surface; and a third semiconductor region of the second conductivity type formed in the semiconducor substrate from the side of its major surface and having a marginal edge extending downwardly from the major surface such that the latter marginal edge is substantially aligned with the marginal edge of the second conductive layer, the third semiconductor region extending from its marginal edge away from the second conductive layer; and wherein a second insulated gate field effect transistor is constituted using the second conductive layer as its gate electrode, that region of the second insulation layer underlying the gate electrode as its gate insulating layer, the third semiconductor region as either one of its source and drain regions, and the second semiconductor region as the other of its source and drain regions.
Claim 7
Dependent Claim
57 words
A semiconductor device according to claim 5 wherein the layer member includes a third conductive layer extending on the second semiconductor region and a third insulating layer formed on first and second surfaces of the third conductive layer, the surface of the third insulating layer forming the first and second insulating side surfaces of the layer member.
Claim 8
Dependent Claim
82 words
A semiconductor device according to claim 5 wherein the layer member includes a resistance layer extending on the second semiconductor region and a third insulating layer extending on first and second side surfaces of the resistance layer, the surface of the third insulating layer forming the first insulating side surfaces of the layer member, and the resistance layer constituting a resistance element coupled with the other of the source and drain regions of the first and second insulated gate field effect transistors.
Claim 9
Dependent Claim
105 words
A semiconductor device according to claim 5 wherein the layer member includes a third conductive layer extending on the second semiconductor region, a resistance layer formed on the third conductive layer and a third insulating layer formed on first and second side surfaces of the third conductive layer and the resistance layer, the surface of the third insulating layer forming the first and second insulating side surfaces of the layer member, and the resistance layer constituting a first resistance element coupled with the other of the source and drain regions of the first and second insulated gate field effect transistors through the third conductive layer.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-03-01 | 1991-08-31 | 1992-03-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-03-01 | 1995-08-31 | 1996-03-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-03-01 | 1999-08-31 | 2000-03-01 | $7700.00 | Window Closed / Lapsed |