US4726023A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Determination of testability of combined logic end memory by ignoring memory
Assignee: International Business Machines Corp
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Filing: 1986-05-14
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Granted: 1988-02-16
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Expires: 2006-05-14
Abstract
Abstract A method of bounding, from above and below, the probability of uncovering a fault in a logic portion of an integrated circuit having embedded memory. The circuit must be designed according to a specified set of design rules. Then one or more probabilities of fault exposure is calculated for a modified system with the memory portion removed, with its inputs directly connected to its outputs. This probability can be related, by provided relations, to upper and lower bounds of the fault exposure in the unmodified system. The relationships rely upon how the logic portions process given test vectors to control the unremoved memory portion.
Inventors
- 👤 John L. Carter
- 👤 Leendert M. Huisman
- 👤 Thomas W. Williams
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 03:53
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/22; G06F11/26; G11; G11C; G11C29/00; G11C29/54
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
194 words
A method for bounding fault exposure of faults in the logic part of a combined logic and memory system tested by a set of input test vectors, comprising the steps of: removing a portion comprising memory from a combined logic and memory system; connecting one or more data inputs that were connected to said memory portion before it was removed to corresponding data outputs that were connected to said memory portion before it was removed; determining at least one first probability of exposure of a fault in a logic portion of said system by a set of input test vectors applied to said system modified by said removing and connecting steps; calculating at least one of an upper and a lower bound of a second probability of exposure of said fault in said system unmodified by said removing and connecting steps, said upper and lower bounds of said second probability being dependent upon said at least one first probability and said set of input test vectors; and deciding if said logic and memory system is testable by comparing said at least one of an upper and lower bound against at least one predetermined probability.
Claim 2
Independent Claim
194 words
A method for bounding fault exposure of faults in the logic part of a combined logic and memory system tested by a set of input test vectors, comprising the steps of: removing a portion comprising memory from a combined logic and memory system; connecting one or more data inputs that were connected to said memory portion before it was removed to corresponding data outputs that were connected to said memory portion before it was removed; determining at least one first probability of exposure of a fault in a logic portion of said system by a set of input test vectors applied to said system modified by said removing and connecting steps; calculating at least one of an upper and a lower bound of a second probability of exposure of said fault in said system unmodified by said removing and connecting steps, said upper and lower bounds of said second probability being dependent upon said at least one first probability and said set of input test vectors; and deciding if said logic and memory system is testable by comparing said at least one of an upper and lower bound against at least one predetermined probability.
Claim 3
Dependent Claim
130 words
A method as recited in claim 1, wherein said logic portion comprises: a pre-logic section receiving inputs and providing signals to said data inputs of said unremoved memory portion; a post-logic section receiving primary inputs and signals from said data outputs of said unremoved memory portion and providing outputs from said system; and a control and addressing section receiving primary inputs and signals from said data outputs of said unremoved memory portion and providing outputs from said system; and a control and addressing section receiving primary inputs and providing control and addressing signals to said unremoved memory portion, there being no other connections between said pre-logic section, and post-logic section and said control and addressing section; and wherein said set of input test vectors are applied to said primary inputs.
Claim 4
Dependent Claim
113 words
A method as recited in claim 2, wherein said first probability is a probability of exposing said fault when said memory portion in said system with said memory portion being unremoved is being read; and wherein said calculating step includes calculating said lower bound and includes the steps of: determining a first number of input test vectors in said set which causes said control and addressing section to control said unremoved memory portion to be read from any location in said memory portion that has been written to since the last reading of said any location; and equating said lower bound with an algebraic combination of said first probability and said first number.
Claim 5
Dependent Claim
101 words
A method as recited in claim 2, wherein said at least one first probability comprises a third probability of exposing said fault when said unremoved memory portion is being read and a fourth probability of exposing said fault when said unremoved memory portion is not being read; and upper bound and includes the steps of: determining a second number of input test vectors in said set which causes said control and addressing section to control said unremoved memory portion to be read; and equating said upper bound with an algebraic combination of said third and fourth probabilities and said second number.
Claim 6
Dependent Claim
101 words
A method as recited in claim 1, wherein said logic portion comprises: a pre-logic section receiving primary inputs and providing signals to said data inputs of said unremoved memory portion; a post-logic section and from said data outputs of said unremoved memory portion and providing outputs from said system; and a control and addressing section receiving primary inputs and providing control and addressing signals to said unremoved memory portion, there being no other connections between said pre-logic section, said post-logic section and said control and addressing section; and wherein said set of input test vectors are applied to said primary inputs.
Claim 7
Dependent Claim
103 words
A method as recited in claim 1, wherein said logic portion comprises: a pre-logic section receiving primary inputs and providing signals to said data inputs of said unremoved memory portion; a post-logic section receiving signals from said pre-logic section and from said data outputs of said unremoved memory portion and providing outputs from said system; and a control and addressing section receiving primary inputs and providing control and addressing signals to said unremoved memory portion, and providing signals to only one of said pre-logic section and said post-logic section; and wherein said set of input test vectors are applied to said primary inputs.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-02-15 | 1991-08-17 | 1992-02-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-02-15 | 1995-08-17 | 1996-02-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-02-15 | 1999-08-17 | 2000-02-16 | $7700.00 | Window Closed / Lapsed |