US4326290A
Expired / Lapsed
US
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Means and methods for monitoring the storage states of a memory and other storage devices in a digital data processor
Assignee: Unisys Corp
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Filing: 1979-10-16
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Granted: 1982-04-20
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Expires: 1999-10-16
Abstract
Abstract The internal states of a memory and other storage devices within a digital data processing system are made accessible for monitoring purposes using variable mode multi-bit shift register storage devices which are also used for the input-output register of the memory to be monitored. The inputs and outputs of the shift register storage devices are interconnected by gating means which may be selectably controlled to form separately selectable serial strings along which the bits of a selected string may be caused to be shifted to a monitoring unit for monitoring, diagnosing and/or correcting purposes and then returned, via the string, to their original locations in the respective shift register storage devices of the selected string, after which normal data processing operations can be resumed. Selectable storage states within the memory are made accessible by causing the monitoring unit to load the memory address register with a selected address for reading out the selected memory storage states which are to be monitored into the memory input-output register. The string containing the memory input-output register is then selected and the states thereof serially shifted to the monitoring unit for monitoring purposes. Corrections are made by returning corrected values, via the string, to the memory input-output register and then writing these corrected values into the memory at the addressed location.
Inventors
- 👤 Sheila G. Davis
- 👤 Robert E. Franks
- 👤 Alfred J. De Santis
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 05:12
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/22; G06F11/2205; G06F11/2236; G06F11/07; G06F11/0703; G06F11/0706; G06F11/0727; G06F11/073; G06F11/30; G06F11/3003; G06F11/3024; G06F11/3089; G11; G11C; G11C29/00; G11C29/04; G11C29/08; G11C29/12; G11C29/18; G11C29/30; G11C29/32; G06F11/2294
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
242 words
In a digital data processing system, the combination comprising: a selectively addressable memory; addressing means for said memory; a memory output register comprising a plurality of multiple bit storage devices; said memory being operative to read out selected storage states at locations selectd by said addressing means into said memory output register; a plurality of multiple bit storage devices in addition to those comprising said memory output register; and logic circuitry interconnecting said storage devices including those comprising said memory output register for the performance of data processing operations by said system; said logic circuitry including gating means for interconnecting said storage devices including those comprising said memory output register into a plurality of separately selectable strings; and monitoring means for performing monitoring of digital data applied thereto from a selected string; said monitoring means including means providing a memory address for said addressing means for use in reading out selected memory states into said memory output register; said monitoring means also including means for selectably generating one of a plurality of monitor enable signals along with a predetermined plurality of monitor clock signals which are applied to said gating means and to the storage devices of a selected string corresponding to the applied monitor enable signal so as to cause the states thereof to be propagated to and from said monitoring means with the storage devices of the selected string being returned to (their original) states determined by said monitoring means.
Claim 2
Dependent Claim
242 words
In a digital data processing system, the combination comprising: a selectively addressable memory; addressing means for said memory; a memory output register comprising a plurality of multiple bit storage devices; said memory being operative to read out selected storage states at locations selectd by said addressing means into said memory output register; a plurality of multiple bit storage devices in addition to those comprising said memory output register; and logic circuitry interconnecting said storage devices including those comprising said memory output register for the performance of data processing operations by said system; said logic circuitry including gating means for interconnecting said storage devices including those comprising said memory output register into a plurality of separately selectable strings; and monitoring means for performing monitoring of digital data applied thereto from a selected string; said monitoring means including means providing a memory address for said addressing means for use in reading out selected memory states into said memory output register; said monitoring means also including means for selectably generating one of a plurality of monitor enable signals along with a predetermined plurality of monitor clock signals which are applied to said gating means and to the storage devices of a selected string corresponding to the applied monitor enable signal so as to cause the states thereof to be propagated to and from said monitoring means with the storage devices of the selected string being returned to (their original) states determined by said monitoring means.
Claim 3
Dependent Claim
44 words
The invention in accordance with claim 1, wherein (said) the particular predetermined plurality of monitor clock signals (are chosen so as to be equal to the) generated by said monitoring means is determined by the total number of bits contained in the selected string.
Claim 4
Dependent Claim
27 words
The invention in accordance with claim 1, wherein said monitoring means includes means for changing as well as monitoring the bits of the selected string applied thereto.
Claim 5
Dependent Claim
37 words
The invention in accordance with claim 3, wherein said monitoring means further includes means for selectively causing bits returned to said memory output register from said monitoring means to be written into selected locations of said memory.
Claim 6
Dependent Claim
35 words
The invention in accordance with claim 4, wherein said monitoring means includes means for determining whether the bits of the applied string are correct and if not for returning corrected bits to said storage devices.
Claim 7
Dependent Claim
82 words
The invention in accordance with claim 1, 2, 3, 4, or 5, wherein said gating means is responsive to a monitor enable signal to cause interconnection of the inputs and outputs of a predetermined plurality of storage devices corresponding to the applied monitor enable signal so as to form a serial string coupled to said monitoring means and along which string the bits constituting the states of the storage devices in the string are shifted in response to said monitor clock signals.
Claim 8
Dependent Claim
19 words
The invention in accordance with claim 6, wherein the memory output register storage devices are in the same string.
Claim 9
Dependent Claim
31 words
The invention in accordance with claim 7, wherein said addressing means also comprises a plurality of storage devices which are in the same string as said memory output register storage devices.
Claim 10
Dependent Claim
156 words
The invention in accordance with claim 1, 2, 3, 4 or 5, wherein said storage devices including said memory output register storage devices are provided using variable mode shift register storage devices, each shift register storage device having a clock signal input, a plurality of inputs for receiving digital data to be stored in response to an applied clock signal, a corresponding plurality of outputs providing for the outputting of the stored digital data, a shift input for receiving digital data for serial shifting through the shift register storage device in response to applied clock signals, and at least one mode control input for receiving mode control data for determining whether the shift register storage device is to operate in a normal mode in which it serves to provide digital storage for said data processing system or is to operate in a shift mode in which data applied to its shift input is serially shifted therethrough.
Claim 11
Dependent Claim
81 words
The invention in accordance with claim 9, wherein said gating means is responsive to a monitor enable signal to cause interconnection of a predetermined plurality of said variable mode shift register storage devices corresponding to the applied monitor enable signal so as to form a serial string coupled to said monitoring means and along which string the bits constituting the states of the stored data are shifted in response to applied clock signals and mode control data indicating shift mode operation.
Claim 12
Dependent Claim
42 words
The invention in accordance with claim 9, wherein said monitoring means includes means for applying mode control data to said memory output register storage devices to provide normal mode operation thereof for receiving said selected storage states read out from said memory.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-04-19 | 1985-10-19 | 1986-04-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-04-19 | 1989-10-19 | 1990-04-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-04-19 | 1993-10-19 | 1994-04-20 | $7700.00 | Window Closed / Lapsed |