Architecture for a fast frame store using dynamic RAMS

Claim 1

A frame store apparatus for storing digital images formed from data words, each word having a predetermined number of data bits, said apparatus comprising: (a) memory means including at least four selectable memory banks, each bank having a plurality of memory sections, each section having a number of DRAMs equal to said predetermined number of data bits of a data word, each DRAM having refreshable bit cells; (b) input buffer means for receiving incoming data at a high system rate data and holding a predetermined number of data words and then transferring each such data word at a slower frame store rate in parallel to a particular one of said selected memory banks with each data bit being stored in one of the particular section's DRAMs; (c) output buffer means effective while said input buffer means is transferring data to the particular memory bank for receiving data in parallel from the sections of another selected memory bank at the slower frame store rate and holding a predetermined number of data words and then transferring each such data word in parallel at the higher system rate; and (d) a single refresh circuit for causing the refresh of bit cells of a plurality of DRAMs in at least one unselected memory bank simultaneously with the transfer of data to or from selected memory banks.