Patent US4722130A successfully refreshed from Google Patents.
US4722130A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of manufacturing a semiconductor device
Assignee: Toshiba Corp
•
Filing: 1987-02-17
•
Granted: 1988-02-02
•
Expires: 2007-02-17
Abstract
Abstract Disclosed is a method of manufacturing a semiconductor device which comprises the step of forming grooves in the form of a grid on the upper surface of a semiconductor wafer formed with elements, the step of grinding or polishing the underside of the semiconductor wafer to thereby reduce the thickness thereof, the step of applying a first single-sided, self-adhesive sheet onto the underside of the semiconductor wafer, and the step of stretching the second single-sided, self-adhesive sheet so as to space out each other a multiplicity of semiconductor chips divided along the gridlike grooves of the semiconductor wafer. Each semiconductor chip is picked up and mounted on a lead frame.
Inventors
- 👤 Takashi Kimura
- 👤 Toshihiro Kato
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 21:26
CPC Classifications
H; H10; H10P; H10P54/00; B; B28; B28D; B28D1/00; B28D1/003; B28D5/00; B28D5/0058; B28D5/0082; H10D; H10D62/00; H10D62/10; H10D62/117; H10P52/00; H10P72/00; H10P72/70; H10P72/74; H10P72/7402; H10P72/7416; H10P72/7422; H10W; H10W72/00; H10W72/01; H10W72/013; H10W72/01331; H10W72/071; H10W72/073; H10W72/07331; H10W72/07337; H10W72/30; H10W72/351; H10W72/353; H10W72/354; Y; Y10; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49117; Y10T29/49124; Y10T29/49155; Y10T29/49789; Y10T29/4979; Y10T29/4981
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
111 words
A method of manufacturing a semiconductor device comprising forming grooves in the form of a grid in an upper surface of a semiconductor wafer formed with elements, applying a first single-sided self-adhesive sheet onto the upper surface of said semiconductor wafer formed with said grooves to reinforce said wafer, after forming said grooves and applying said first sheet grinding or polishing an underside of said semiconductor wafer to reduce the thickness thereof, applying a second single-sided selfadhesive sheet onto the underside of said semiconductor wafer and stretching said second single-sided self-adhesive sheet to space out from each other a multiplicity of semiconductor chips divided along the grooves of said semiconductor wafer.
Claim 2
Independent Claim
111 words
A method of manufacturing a semiconductor device comprising forming grooves in the form of a grid in an upper surface of a semiconductor wafer formed with elements, applying a first single-sided self-adhesive sheet onto the upper surface of said semiconductor wafer formed with said grooves to reinforce said wafer, after forming said grooves and applying said first sheet grinding or polishing an underside of said semiconductor wafer to reduce the thickness thereof, applying a second single-sided selfadhesive sheet onto the underside of said semiconductor wafer and stretching said second single-sided self-adhesive sheet to space out from each other a multiplicity of semiconductor chips divided along the grooves of said semiconductor wafer.
Claim 3
Dependent Claim
35 words
A method of manufacturing a semiconductor device according to claim 1, which further comprises forming a semi-hardened resin bonding layer, intended for use in diebonding, on said ground or polished underside of said semiconductor wafer.
Claim 4
Dependent Claim
33 words
A method of manufacturing a semiconductor device according to claim 2, which further comprises forming a metal thin film between the ground or polished underside of said semiconductor wafer and said bonding layer.
Claim 5
Dependent Claim
28 words
A method of manufacturing a semiconductor device according to claim 1, which further comprises peeling off said first self-adhesive sheet after said second self-adhesive sheet has been applied.
References Cited (Backward Citations)
US3040489A
Cited
US3488835A
Cited
US3633269A
Cited
US3727282A
Cited
US3636618A
Cited
US4321747A
Cited
US4519168A
Cited
US4451972A
Cited
US4445956A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-02-01 | 1991-08-03 | 1992-02-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-02-01 | 1995-08-03 | 1996-02-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-02-01 | 1999-08-03 | 2000-02-02 | $7700.00 | Window Closed / Lapsed |