Method for manufacturing a semiconductor device

Claim 1

A method of manufacturing a semiconductor device having floating and control gates which further includes source and drain regions, a channel region, and a composite insulating layer provided between said floating and control gates, said method comprising the steps of: selecting first and second regions on a semiconductor substrate of a first conductivity type, said source and drain regions being formed in said first and second regions; forming a field insulating layer surrounding an active region including said first and second regions; forming a first SiO 2 (silicon dioxide) layer covering said active region; forming a first polysilicon layer covering said first SiO 2 layer and said field insulating layer; patterning said first polysilicon layer so as to have a width corresponding to the width of said floating gate, said width being the length in the channel-width direction; forming a multilayered insulating layer on said first polysilicon layer from which said composite insulating layer is formed; forming a second polysilicon layer on said multilayered insulating layer; forming a resist pattern on said second polysilicon layer, said resist pattern having a length corresponding to that of said composite insulating layer, said length being the length in the channel-length direction; effecting an etching, using said resist pattern as a mask, for forming said control gate, said composite insulating layer and said floating gate, so as to have an equal length; shortening the lengths of said control and floating gates; and doping an impurity of second conductivity type into said first and second regions for forming said source and drain regions.

Claim 2

A method of manufacturing a semiconductor device having floating and control gates which further includes source and drain regions, a channel region, and a composite insulating layer provided between said floating and control gates, said method comprising the steps of: selecting first and second regions on a semiconductor substrate of a first conductivity type, said source and drain regions being formed in said first and second regions; forming a field insulating layer surrounding an active region including said first and second regions; forming a first SiO 2 (silicon dioxide) layer covering said active region; forming a first polysilicon layer covering said first SiO 2 layer and said field insulating layer; patterning said first polysilicon layer so as to have a width corresponding to the width of said floating gate, said width being the length in the channel-width direction; forming a multilayered insulating layer on said first polysilicon layer from which said composite insulating layer is formed; forming a second polysilicon layer on said multilayered insulating layer; forming a resist pattern on said second polysilicon layer, said resist pattern having a length corresponding to that of said composite insulating layer, said length being the length in the channel-length direction; effecting an etching, using said resist pattern as a mask, for forming said control gate, said composite insulating layer and said floating gate, so as to have an equal length; shortening the lengths of said control and floating gates; and doping an impurity of second conductivity type into said first and second regions for forming said source and drain regions.

Claim 7

A method of manufacturing a semiconductor device having floating and control gates which further includes source and drain regions, a channel region, and a composite insulating layer provided between said floating and control gates, said method comprising the steps of: selecting first and second regions on a semiconductor substrate of a first conductivity type, said source and drain regions being formed in said first and second regions; forming a field insulating layer surrounding an active region including said first and second regions; forming a first SiO 2 (silicon dioxide) layer covering said active region; forming a laminated layer including a first polysilicon layer covering said first SiO 2 layer and said field insulating layer, a second SiO 2 layer covering said first polysilicon layer, a silicon nitride layer covering said second SiO 2 layer, and a third SiO 2 layer covering said silicon nitride layer; patterning said laminated layer so as to have a width corresponding to the width of said floating gate, said width being the length in the channel-width direction; making the ends of said patterned silicon nitride layer extend in the channel-width direction beyond the ends of said patterned first polysilicon layer by a thermal treatment; forming a second polysilicon layer on said laminated layer; forming a resist pattern on said second polysilicon layer, said resist pattern having a length corresponding to that of said composite insulating layer; etching, by anisotropic etching method and using said resist pattern as a mask, said second polysilicon layer, said third SiO 2 layer, said silicon nitride layer, said second SiO 2 layer and said first polysilicon layer; shortening the lengths of said second polysilicon layer and said first polysilicon layer; and doping an impurity of a second conductivity type into said first and second regions for forming said source and drain regions.

Claim 8

A method of manufacturing a semiconductor device having floating and control gates which further includes source and drain regions, a channel region, and a composite insulating layer provided between said floating and control gates, said method comprising the steps of: selecting first and second regions on a semiconductor substrate of a first conductivity type, said source and drain regions being formed in said first and second regions; forming a field insulating layer surrounding an active region including said first and second regions; forming a first SiO 2 (silicon dioxide) layer covering said active region; forming a laminated layer including a first polysilicon layer covering said first SiO 2 layer and said field insulating layer, a second SiO 2 layer covering said first polysilicon layer, a silicon nitride layer covering said second SiO 2 layer, and a third SiO 2 layer covering said silicon nitride layer; patterning said laminated layer so as to have a width corresponding to the width of said floating gate, said width being the length in the channel-width direction; making the ends of said patterned silicon nitride layer extend in the channel-width direction beyond the ends of said patterned first polysilicon layer by a thermal treatment; forming a second polysilicon layer on said laminated layer; forming a resist pattern on said second polysilicon layer, said resist pattern having a length corresponding to that of said composite insulating layer; etching, by anisotropic etching method and using said resist pattern as a mask, said second polysilicon layer, said third SiO 2 layer, said silicon nitride layer, said second SiO 2 layer and said first polysilicon layer; shortening the lengths of said second polysilicon layer and said first polysilicon layer; and doping an impurity of a second conductivity type into said first and second regions for forming said source and drain regions.

Claim 9

A method of manufacturing a semiconductor device having floating and control gates which further includes source and drain regions, a channel region, and a composite insulating layer provided between said floating and control gates, said method comprising the steps of : selecting first and second regions on a semiconductor substrate of a first conductivity type, said source and drain regions being formed in said first and second regions; forming a field insulating layer surrounding an active region including said first and second regions; forming a first SiO 2 layer covering said active region; forming a laminated layer, including a first polysilicon layer forming one of said floating and control gates covering said first SiO 2 layer and covering said field insulating layer, a second SiO 2 layer covering said first polysilicon layer, a silicon nitride layer covering said second SiO 2 layer, and a third SiO 2 layer covering said silicon nitride layer; patterning said laminated layer so as to have a width corresponding to the width of one of said floating and control gates, said width extending in the channel-width direction; making the ends of said patterned silicon nitride layer extend in the channel-width direction beyond the ends of said patterned first polysilicon layer by a thermal treatment; and forming the other of said floating and control gates on said patterned laminated layer.

Claim 10

A method of manufacturing a semiconductor device having floating and control gates which further includes source and drain regions, a channel region, and a composite insulating layer provided between said floating and control gates, said method comprising the steps of : selecting first and second regions on a semiconductor substrate of a first conductivity type, said source and drain regions being formed in said first and second regions; forming a field insulating layer surrounding an active region including said first and second regions; forming a first SiO 2 layer covering said active region; forming a laminated layer, including a first polysilicon layer forming one of said floating and control gates covering said first SiO 2 layer and covering said field insulating layer, a second SiO 2 layer covering said first polysilicon layer, a silicon nitride layer covering said second SiO 2 layer, and a third SiO 2 layer covering said silicon nitride layer; patterning said laminated layer so as to have a width corresponding to the width of one of said floating and control gates, said width extending in the channel-width direction; making the ends of said patterned silicon nitride layer extend in the channel-width direction beyond the ends of said patterned first polysilicon layer by a thermal treatment; and forming the other of said floating and control gates on said patterned laminated layer.

Claim 11

A method of manufacturing a semiconductor device having floating and control gates which further includes source and drain regions, a channel region, and a composite insulating layer provided between said floating and control gates, said method comprising the steps of: selecting first and second regions on a semiconductor substrate of a first conductivity type, said source and drain regions being formed in said first and second regions; forming a field insulating layer surrounding an active region including said first and second regions; forming a first SiO 2 layer covering said active region; forming a laminated layer, including a first polysilicon layer forming one of said floating and control gates covering said first SiO 2 layer and covering said field insulating layer, a second SiO 2 layer covering said first polysilicon layer, a silicon nitride layer covering said second SiO 2 layer, and a third SiO 2 layer covering said silicon nitride layer; patterning said laminated layer so as to have a length corresponding to the length of one of said floating and control gates, said length extending in the channel-length direction; making the ends of said patterned silicon nitride layer extend in the channel-length direction beyond the ends of said patterned first polysilicon layer by a thermal treatment; and forming the other of said floating and control gates on said patterned laminated layer.

Claim 12

A method of manufacturing a semiconductor device having floating and control gates which further includes source and drain regions, a channel region, and a composite insulating layer provided between said floating and control gates, said method comprising the steps of: selecting first and second regions on a semiconductor substrate of a first conductivity type, said source and drain regions being formed in said first and second regions; forming a field insulating layer surrounding an active region including said first and second regions; forming a first SiO 2 layer covering said active region; forming a laminated layer, including a first polysilicon layer forming one of said floating and control gates covering said first SiO 2 layer and covering said field insulating layer, a second SiO 2 layer covering said first polysilicon layer, a silicon nitride layer covering said second SiO 2 layer, and a third SiO 2 layer covering said silicon nitride layer; patterning said laminated layer so as to have a length corresponding to the length of one of said floating and control gates, said length extending in the channel-length direction; making the ends of said patterned silicon nitride layer extend in the channel-length direction beyond the ends of said patterned first polysilicon layer by a thermal treatment; and forming the other of said floating and control gates on said patterned laminated layer.