US4514897A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Electrically programmable floating gate semiconductor memory device
Assignee: Texas Instruments Inc
•
Filing: 1984-04-26
•
Granted: 1985-05-07
•
Expires: 2004-04-26
Abstract
Abstract An N-channel, double level poly, MOS read only memory or ROM array is electrically programmable by floating gates positioned beneath control gates formed by row address lines. The cells may be electrically programmed by applying selected voltages to the source, drain, control gate and substrate; the floating gate is charged through an insulator between the floating gate and the channel. A simplified process for fabrication of the devices eliminates photoresist and implant steps yet produces improved characteristics in the form of higher gain and lower body effect.
Inventors
- 👤 Te-Long Chiu
- 👤 Jih-Chang Lien
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 08:34
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/13; H10D62/149; H10D62/151; G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0408; G11C16/0416; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H10D30/684; H10D30/685
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
173 words
A method of making a semiconductor device comprising the steps of: depositing a first conductive layer on a face of a semiconductor body of one type over an insulating coating, and patterning said first conductive layer to leave an electrode, depositing a second conductive layer on said face over an insulating coating and over said first conductive layer, with insulating coating between the first and second layers, and patterning said second layer to leave an electrode, introducing conductivity determining impurity of the opposite type into the body in self-alignment with the first and second conductive layers, the improvement comprising the step of introducing conductivity determining impurity of said one type into said body in self-alignment with the first conductive layer using one of said conductive layers as a mask, to form a region more heavily doped than the body, said region extending partially beneath the first conductive layer but not extending completely from one side of said electrode of the first layer to the other side of said electrode of the first layer.
Claim 2
Independent Claim
173 words
A method of making a semiconductor device comprising the steps of: depositing a first conductive layer on a face of a semiconductor body of one type over an insulating coating, and patterning said first conductive layer to leave an electrode, depositing a second conductive layer on said face over an insulating coating and over said first conductive layer, with insulating coating between the first and second layers, and patterning said second layer to leave an electrode, introducing conductivity determining impurity of the opposite type into the body in self-alignment with the first and second conductive layers, the improvement comprising the step of introducing conductivity determining impurity of said one type into said body in self-alignment with the first conductive layer using one of said conductive layers as a mask, to form a region more heavily doped than the body, said region extending partially beneath the first conductive layer but not extending completely from one side of said electrode of the first layer to the other side of said electrode of the first layer.
Claim 3
Dependent Claim
25 words
A method according to claim 1 wherein the first and second conductive layers are polycrystalline silicon, and the semiconductor device is an electrically programmable memory.
Claim 4
Dependent Claim
21 words
A method according to claim 2 wherein the insulating coating is silicon oxide and the semiconductor body is P type silicon.
Claim 5
Dependent Claim
29 words
A method according to claim 3 wherein the step of introducing impurity is performed on one side of said one of the layers but not on the other side.
Claim 6
Dependent Claim
15 words
A method according to claim 4 wherein the first and second conductive layers are self-aligned.
References Cited (Backward Citations)
US4222063A
Cited
US4208780A
Cited
US4214359A
Cited
US4282646A
Cited
US4376947A
Cited
US4317273A
Cited
EP0071335A2
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-05-06 | 1988-11-05 | 1989-05-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-05-06 | 1992-11-05 | 1993-05-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-05-06 | 1996-11-05 | 1997-05-07 | $7700.00 | Window Closed / Lapsed |