TTL compatible CMOS input buffer

Claim 1

A TTL to CMOS level conversion buffer circuit including a first field effect transistor of one conductivity type and a second field effect transistor of the other conductivity type, each of said first and second transistors having a main current conducting path with a first and second end, a third field effect transistor having a main current conducting path, means for coupling the first and second ends of the main current conducting path of the third transistor in series between the first ends of the main current conducting paths of the first and second transistors, respectively, and means for coupling the second ends of the main current conducting paths of the first and second transitors to first and second terminals of a power supply, each of the first, second and third transistors including a control electrode, the signal level on which controls current flow through the main current conducting path thereof, means for coupling the control electrodes of the first and second transistors to an output of a TTL circuit, an output signal of which is to be converted to CMOS logic level, means for coupling the main current conducting path of the third transistor to an output of the buffer circuit, and means for coupling the control electrode of the third transistor to a voltage source having an absolute magnitude which is greater than the voltage on the control electrodes of the first and second transistors, and further including a fourth field effect transistor of one conductivity type and a fifth field effect transistor of the other conductivity type, each of said fourth and fifth transistors having a main current conducting path with first and second ends and a control electrode, means for coupling the first ends of the fourth and fifth transistors to each other and to the output of the buffer circuit and means for coupling the second ends of the main current conducting paths of the fourth and fifth transistors to the first and second terminals of the power supply, respectively, means for coupling the control electrodes of the fourth and fifth transistors to the output of the TTL circuit, and wherein said means for coupling the main current conducting path of the third transistor to the output of the buffer circuit comprises a bipolar transistor having a main current conducting path and a control electrode, wherein said control electrode of the bipolar transistor is coupled to the second end of the main current conducting path of the third transistor and the main current conducting path of the bipolar transistor is connected between a source of voltage and the output of the buffer circuit.