Patent US4440137A successfully refreshed from Google Patents.
Patent US4717835A successfully refreshed from Google Patents.
US4717835A
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Semiconductor integrated circuit with detection circuit for address signal change
Assignee: Fujitsu Ltd
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Filing: 1987-01-16
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Granted: 1988-01-05
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Expires: 2007-01-16
Abstract
Abstract A semiconductor integrated circuit with a detection circuit for detecting an address signal change comprises a plurality of gate circuits, and a plurality of delay circuits able to be reset, and each delay circuit is reset when the address signal or an inversion signal thereof is at a predetermined polarity and level. Whereby, the semiconductor integrated circuit can generate a pulse having a pulse width no shorter than a predetermined time interval if a change equivalent to the address change is caused by successive noise.
Inventors
- 👤 Atsushi Takeuchi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 20:57
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; H; H03; H03K; H03K5/00; H03K5/01; H03K5/04; H03K5/13; H03K5/153; H03K5/1534
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
198 words
A semiconductor integrated circuit with a detection circuit for detecting a change of an input signal comprising: a first gate circuit for receiving an input signal at one input thereof; a second gate circuit for receiving an inverted input signal at one input thereof; a third gate circuit for receiving outputs of said first gate circuit and said second gate circuit; a first resettable delay circuit for receiving an output of said second gate circuit, to delay said output of said second gate circuit for a predetermined time interval, and to supply an output thereof to another input of said first gate circuit; and a second resettable delay circuit for receiving an output of said first gate circuit, to delay said output of said first gate circuit for a predetermined time interval, and to supply an output thereof to another input of said second gate circuit; said first resettable delay circuit receiving the input signal at a reset input and being reset in response to a change of the input signal; said second resettable delay circuit receiving the inverted input signal at a reset input and being reset in response to a change of the inverted input signal.
Claim 2
Dependent Claim
198 words
A semiconductor integrated circuit with a detection circuit for detecting a change of an input signal comprising: a first gate circuit for receiving an input signal at one input thereof; a second gate circuit for receiving an inverted input signal at one input thereof; a third gate circuit for receiving outputs of said first gate circuit and said second gate circuit; a first resettable delay circuit for receiving an output of said second gate circuit, to delay said output of said second gate circuit for a predetermined time interval, and to supply an output thereof to another input of said first gate circuit; and a second resettable delay circuit for receiving an output of said first gate circuit, to delay said output of said first gate circuit for a predetermined time interval, and to supply an output thereof to another input of said second gate circuit; said first resettable delay circuit receiving the input signal at a reset input and being reset in response to a change of the input signal; said second resettable delay circuit receiving the inverted input signal at a reset input and being reset in response to a change of the inverted input signal.
Claim 3
Dependent Claim
21 words
A semiconductor integrated circuit as set forth in claim 1, wherein said first, second, and third gate circuits are NAND gates.
Claim 4
Dependent Claim
21 words
A semiconductor integrated circuit as set forth in claim 1, wherein said first, second, and third gate circuits are NOR gates.
Claim 5
Dependent Claim
198 words
A semiconductor integrated circuit as set forth in claim 2, wherein each resettable delay circuit comprises a capacitor, a resistance, first, second, third, and fourth transistors, and an inverter; said capacitor being charged to a high level through said first transistor when said first transistor receives at a gate thereof a low level signal from said input signal or said inverted input signal; said capacitor being charged to a high level through said second transistor when said second transistor receives at a gate thereof a low level signal from an output of a gate circuit connected to an output of said other resettable delay circuit; an electric charge in said capacitor being discharged through said third transistor, said fourth transistor, and said resistance when said third transistor receives at a gate thereof a high level signal from said input signal or said inverted input signal, and when said fourth transistor receives at a gate thereof a high level signal from said output of said gate circuit connected to said output of said other resettable delay circuit; and a voltage across said capacitor being amplified and inverted by a predetermined threshold through said inverter and supplied as an output.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-01-04 | 1991-07-06 | 1992-01-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-01-04 | 1995-07-06 | 1996-01-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-01-04 | 1999-07-06 | 2000-01-05 | $7700.00 | Window Closed / Lapsed |