Patent US4716307A successfully refreshed from Google Patents.
US4716307A
Expired / Lapsed
US
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Regulated power supply for semiconductor chips with compensation for changes in electrical characteristics or chips and in external power supply
Assignee: Fujitsu Ltd
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Filing: 1986-08-12
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Granted: 1987-12-29
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Expires: 2006-08-12
Abstract
Abstract A semiconductor device having a circuit for regulating the external power supply voltage applied to the chip. When numerous chips are used in an electronic circuit having an external power supply voltage, variations in the electrical characteristics, such as the total power supply current, of each chip, become a problem. According to the present invention, variations in the electrical characteristics can be reduced by compensating the chip-to-chip fluctuations of the conductance of transistors (FETs) contained in an inner circuit disposed on the chip. A dummy transistor having a relatively short channel length is employed as a circuit for detecting the electrical characteristics of the transistors formed on the chip. The voltage drop across the dummy transistor is employed as a representative signal since it is sensitive to variations in the characteristics of the FETs contained in the inner circuit. Regulation of the power supply voltage is performed by a regulating device, usually a transistor, connected in series between the external power supply and the inner circuit. The representative signal is amplified by a regulating signal generating circuit whose output voltage is applied to the regulating device, thereby controlling the conductance of the regulating device.
Inventors
- 👤 Keizo Aoyama
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 06:11
CPC Classifications
G; G05; G05F; G05F1/00; G05F1/10; G05F1/46; G05F1/462; G05F1/465; H; H10; H10D; H10D84/00; H10D84/80; H10D84/82
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
209 words
A semiconductor device having an external power supply line operatively connected to receive an external power supply voltage, comprising: a semiconductor substrate; an inner circuit, formed on said semiconductor substrate, containing a plurality of transistors; voltage regulating means, formed on said substrate, operatively connected to receive the external power supply voltage and operatively connected to said inner circuit, for regulating the external power supply voltage and converting the external power supply voltage to an internal power supply voltage to be applied to said inner circuit; and controlling means, formed on said semiconductor substrate and operatively connected to said voltage regulating means, for controlling said voltage regulating means in accordance with the characteristics of said transistors in said inner circuit so that variations in the electrical characteristics of said transistors are compensated in dependence upon the external power supply voltage, said controlling means comprising: means for providing a representative signal which represents electrical characteristics of said transistors in said inner circuit; means for generating a reference voltage in accordance with the external power supply voltage; and means, operatively connected to said means for providing a representative signal and said means for generating a reference voltage, for generating a regulating signal in accordance with said representative signal and said reference voltage.
Claim 2
Dependent Claim
209 words
A semiconductor device having an external power supply line operatively connected to receive an external power supply voltage, comprising: a semiconductor substrate; an inner circuit, formed on said semiconductor substrate, containing a plurality of transistors; voltage regulating means, formed on said substrate, operatively connected to receive the external power supply voltage and operatively connected to said inner circuit, for regulating the external power supply voltage and converting the external power supply voltage to an internal power supply voltage to be applied to said inner circuit; and controlling means, formed on said semiconductor substrate and operatively connected to said voltage regulating means, for controlling said voltage regulating means in accordance with the characteristics of said transistors in said inner circuit so that variations in the electrical characteristics of said transistors are compensated in dependence upon the external power supply voltage, said controlling means comprising: means for providing a representative signal which represents electrical characteristics of said transistors in said inner circuit; means for generating a reference voltage in accordance with the external power supply voltage; and means, operatively connected to said means for providing a representative signal and said means for generating a reference voltage, for generating a regulating signal in accordance with said representative signal and said reference voltage.
Claim 3
Dependent Claim
23 words
A semiconductor device according to claim 1, wherein said transistors in said inner circuit are a metal insulator semiconductor field effect transistors (MISFETs).
Claim 4
Dependent Claim
77 words
A semiconductor device according to claim 1, operatively connected to a power supply line, wherein said means for providing a representative signal comprises: a dummy transistor operativley connected to the external power supply line; and a load transistor connected in series between said dummy transistor and the power supply line, a voltage at a node between said dummy transistor and said load transistors being input to said means for generating a regulating signal as said representative signal.
Claim 5
Dependent Claim
99 words
A semiconductor device according to claim 1, operatively connected to a power supply line, wherein said means for generating a regulating signal comprises: first load means operatively connected to the external power supply line; an amplifying transistor operatively connected in series with said first load means; and second load means, operatively connected in series between said amplifying transistor and the power supply line, said representative signal being input to said amplifying transistor, and a voltage at a connection node of said first load means and said amplifying transistor being input to said voltage regulating means as said regulating signal.
Claim 6
Dependent Claim
74 words
A semiconductor device according to claim 1, operatively connected to a power supply line, wherein said means for generating a reference voltage comprises: first and second resistors operatively connected in series, said first resistor connected to the external power supply line and said second resistor connected to the power supply line, a voltage at a node between said first resistor and said second resistor being input to said means for generating a regulating signal.
Claim 7
Dependent Claim
134 words
A semiconductor device according to claim 1, operatively connected to a power supply line, wherein said means for generating a regulating signal comprises: first and second load means connected to the external power supply line; first and second input transistors connected in series to said first and second load means, respectively; and a common transistor commonly connected between said first and second transistors and the power supply line, said representative signal and said reference voltage signal applied to said first and second input transistors, respectively, a voltage at a node between said second load means and said second input transistor being fed back to said common transistor, and a voltage at a node between said first load means and said first input transistor being input to said voltage regulating means as said regulating signal.
Claim 8
Dependent Claim
43 words
A semiconductor device according to claim 1, wherein said transistors in said controlling means, except said dummy transistor, are FETs having channel lengths sufficiently long to make the electrical characteristics of said FETs insensitive to variations in the channel lengths of said FETs.
Claim 9
Dependent Claim
45 words
A semiconductor device according to claim 3 wherein said transistors in said controlling means, except said dummy transistor, are FETs having channel lengths sufficiently long to make the electrical characteristics of said FETs substantially insensitive to any variations in the channel lengths of said FETs.
Claim 10
Dependent Claim
43 words
A semiconductor device according to claim 3, wherein said dummy transistor is an FET having a channel length sufficiently short to make the electrical characteristics of said FET substantially sensitive to variations in the channel length of said FETs in said inner circuit.
Claim 11
Dependent Claim
22 words
A semiconductor device according to claim 3, wherein said transistors in said inner circuit are metal insulator semiconductor field effect transistors (MISFETs).
Claim 12
Dependent Claim
22 words
A semiconductor device according to claim 4, wherein said transistors in said inner circuit are metal insulator semiconductor field effect transistors (MISFETs).
Claim 13
Dependent Claim
43 words
A semiconductor device according to claim 4, wherein said transistors in said controlling means, except said dummy transistor, are FETs having channel lengths sufficiently long to make the electrical characteristics of said FETs insensitive to variations in the channel lengths of said FETs.
Claim 14
Dependent Claim
22 words
A semiconductor device according to claim 5, wherein said transistors in said controlling means are metal insulator semiconductor field effect transistors (MISFETs).
Claim 15
Dependent Claim
43 words
A semiconductor device according to claim 5, wherein said transistors in said controlling means, except said dummy transistor, are FETs having channel lengths sufficiently long to make the electrical characteristics of said FETs insensitive to variations in the channel lengths of said FETs.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-12-28 | 1991-06-29 | 1991-12-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-12-28 | 1995-06-29 | 1995-12-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-12-28 | 1999-06-29 | 1999-12-29 | $7700.00 | Window Closed / Lapsed |