Fabrication of double diffused metal oxide semiconductor transistor

Claim 1

A process for fabricating a double diffused metal oxide semiconductor transistor structure comprising the steps of: sequentially forming on a silicon substrate a thin film of gate oxide, a layer of polysilicon, and a first layer of thermally grown oxide; etching a window through said layers and said thin film whereby said polysilicon layer is configured into gate regions having side walls and a window between said gate regions; implanting nitrogen in said semiconductor substrate window region for forming an oxidation inhibitor to silicon; thermally growing a second layer of silicon oxide over said side walls of said gate regions and over said window forming thereby a thin oxide pad over said window; implanting P-type impurity material below said window; forming silicon nitride over said second layer of thermally grown silicon oxide and patterning by masking and etching said silicon nitride to form spaced regions that define a narrow window therebetween; implanting P+ type impurity material through said narrow window between said gate regions; growing a localized oxide plug over said implanted P+ region by a drive-in diffusion and oxidation cycle; implanting N-type material to form a junction adjacent to said gate region; and opening access to said gate regions for defining metal contact regions.