US4713790A
Expired / Lapsed
US
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Exclusive OR/NOR gate having cross-coupled transistors
Assignee: Motorola Solutions Inc
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Filing: 1985-07-31
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Granted: 1987-12-15
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Expires: 2005-07-31
Abstract
Abstract A CMOS exclusive OR/NOR gate is implemented with cross coupled transistors of the same conductivity type for simultaneously providing both logic signals. The logic gate is characterized by a pair of cross-coupled transistors of the same conductivity type coupled to the outputs thereof for selectively reinforcing the output logic level. One use of the exclusive OR/NOR gate is illustrated by coupling the gate to a switched logic circuit to provide a full adder. Transmission gate steering logic is used to further enhance circuit speed.
Inventors
- 👤 Kevin L. Kloker
- 👤 Ronald H. Cieslak
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 21:19
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/50; G06F7/501; G06F7/503; H; H03; H03K; H03K19/00; H03K19/20; H03K19/21; H03K19/215; G06F2207/00; G06F2207/38; G06F2207/3804; G06F2207/386; G06F2207/3876
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
322 words
A logic gate for receiving first and second input signals at first and second input terminals, respectively, and providing exclusive OR and exclusive NOR signals of the input signals at first and second output terminals, respectively, comprising: first inverter means having an input coupled to the first input terminal, and an output; second inverter means having an input coupled to the second input terminal, and an output; a first transistor of a first conductivity type having a first current electrode coupled to the output of the first inverter means, a second current electrode coupled to the first output terminal, and a control electrode coupled to the second input terminal; a second transistor of the first conductivity type having a first current electrode coupled to the first input terminal, a second current electrode coupled to the second output terminal, and a control electrode coupled to the second input terminal; a third transistor of the first conductivity type having a first current electrode coupled to the first input terminal, a second current electrode coupled to the first output terminal, and a control electrode coupled to the output of the second inverter means; a fourth transistor of the first conductivity type having a first current electrode coupled to the output of the first inverter means, a second current electrode coupled to the second output terminal, and a control electrode coupled to the output of the second inverter means; a fifth transistor of a second conductivity type having a first current electrode coupled to the first output terminal, a second current electrode coupled to a terminal for receiving a power supply voltage, and a control electrode coupled to the second output terminal; and a sixth transistor of the second conductivity type having a first current electrode coupled to the second output terminal, a second current electrode coupled to the terminal for receiving the power supply voltage, and a control electrode coupled to the first output terminal.
Claim 2
Dependent Claim
322 words
A logic gate for receiving first and second input signals at first and second input terminals, respectively, and providing exclusive OR and exclusive NOR signals of the input signals at first and second output terminals, respectively, comprising: first inverter means having an input coupled to the first input terminal, and an output; second inverter means having an input coupled to the second input terminal, and an output; a first transistor of a first conductivity type having a first current electrode coupled to the output of the first inverter means, a second current electrode coupled to the first output terminal, and a control electrode coupled to the second input terminal; a second transistor of the first conductivity type having a first current electrode coupled to the first input terminal, a second current electrode coupled to the second output terminal, and a control electrode coupled to the second input terminal; a third transistor of the first conductivity type having a first current electrode coupled to the first input terminal, a second current electrode coupled to the first output terminal, and a control electrode coupled to the output of the second inverter means; a fourth transistor of the first conductivity type having a first current electrode coupled to the output of the first inverter means, a second current electrode coupled to the second output terminal, and a control electrode coupled to the output of the second inverter means; a fifth transistor of a second conductivity type having a first current electrode coupled to the first output terminal, a second current electrode coupled to a terminal for receiving a power supply voltage, and a control electrode coupled to the second output terminal; and a sixth transistor of the second conductivity type having a first current electrode coupled to the second output terminal, a second current electrode coupled to the terminal for receiving the power supply voltage, and a control electrode coupled to the first output terminal.
Claim 3
Dependent Claim
292 words
An exclusive OR/NOR logic gate for providing substantially simultaneously an exclusive OR and an exclusive NOR of first and second input signals at first and second output terminals, respectively, comprising: first inverter means having an input coupled to a first input terminal, and an output; second inverter means having an input coupled to a second input terminal, and an output; a first transistor of a first conductivity type having a first current electrode coupled to the output of the first inverter means, a second current electrode coupled to the first output terminal, and a control electrode coupled to the second input terminal; a second transistor of the first conductivity type having a first current electrode coupled to the first input terminal, a second current electrode coupled to the second output terminal, and a control electrode coupled to the second input terminal; a third transistor of the first conductivity type having a first current electrode coupled to the first input terminal, a second current electrode coupled to the first output terminal, and a control electrode coupled to the output of the second inverter means; a fourth transistor of the first conductivity type having a first current electrode coupled to the output of the first inverter means, a second current electrode coupled to the second output terminal, and a control electrode coupled to the output of the second inverter means; and a pair of transistors of a second conductivity type, each transistor of the pair having first and second current electrodes coupled between a predetermined one of the first or second output terminals and a power supply terminal, and the pair of transistors having the gates thereof cross-coupled, each gate being coupled to a predetermined one of the second or first output terminals, respectively.
Claim 4
Dependent Claim
292 words
An exclusive OR/NOR logic gate for providing substantially simultaneously an exclusive OR and an exclusive NOR of first and second input signals at first and second output terminals, respectively, comprising: first inverter means having an input coupled to a first input terminal, and an output; second inverter means having an input coupled to a second input terminal, and an output; a first transistor of a first conductivity type having a first current electrode coupled to the output of the first inverter means, a second current electrode coupled to the first output terminal, and a control electrode coupled to the second input terminal; a second transistor of the first conductivity type having a first current electrode coupled to the first input terminal, a second current electrode coupled to the second output terminal, and a control electrode coupled to the second input terminal; a third transistor of the first conductivity type having a first current electrode coupled to the first input terminal, a second current electrode coupled to the first output terminal, and a control electrode coupled to the output of the second inverter means; a fourth transistor of the first conductivity type having a first current electrode coupled to the output of the first inverter means, a second current electrode coupled to the second output terminal, and a control electrode coupled to the output of the second inverter means; and a pair of transistors of a second conductivity type, each transistor of the pair having first and second current electrodes coupled between a predetermined one of the first or second output terminals and a power supply terminal, and the pair of transistors having the gates thereof cross-coupled, each gate being coupled to a predetermined one of the second or first output terminals, respectively.
Claim 5
Dependent Claim
267 words
A logic gate for receiving first and second input signals at first and second input terminals, respectively, and providing exclusive OR and exclusive NOR signals of the input signals at first and second output terminals, respectively, comprising: first inverter means having an input coupled to the first input terminal, and an output; second inverter means having an input coupled to the second input terminal, and an output; a first N-channel transistor having a drain coupled to the output of the first inverter means, a source coupled to the first output terminal, and a gate coupled to the second input terminal; a second N-channel transistor having a drain coupled to the first input terminal, a source coupled to the second output, and a gate coupled to the second input terminal; a third N-channel transistor having a drain coupled to the first input terminal, a source coupled to the first output terminal, and a gate coupled to the output of the second inverter means; a fourth N-channel transistor having a drain coupled to the output of the first inverter means, a source coupled to the second output terminal, and a gate coupled to the output of the second inverter means; a first P-channel transistor having a source coupled to the first output terminal, a drain coupled to a terminal for receiving a power supply voltage, and a gate coupled to the second output terminal; and a second P-channel transistor having a source coupled to the second output terminal, a drain coupled to the terminal for receiving the power supply voltage, and a gate coupled to the first output terminal.
Claim 6
Dependent Claim
267 words
A logic gate for receiving first and second input signals at first and second input terminals, respectively, and providing exclusive OR and exclusive NOR signals of the input signals at first and second output terminals, respectively, comprising: first inverter means having an input coupled to the first input terminal, and an output; second inverter means having an input coupled to the second input terminal, and an output; a first N-channel transistor having a drain coupled to the output of the first inverter means, a source coupled to the first output terminal, and a gate coupled to the second input terminal; a second N-channel transistor having a drain coupled to the first input terminal, a source coupled to the second output, and a gate coupled to the second input terminal; a third N-channel transistor having a drain coupled to the first input terminal, a source coupled to the first output terminal, and a gate coupled to the output of the second inverter means; a fourth N-channel transistor having a drain coupled to the output of the first inverter means, a source coupled to the second output terminal, and a gate coupled to the output of the second inverter means; a first P-channel transistor having a source coupled to the first output terminal, a drain coupled to a terminal for receiving a power supply voltage, and a gate coupled to the second output terminal; and a second P-channel transistor having a source coupled to the second output terminal, a drain coupled to the terminal for receiving the power supply voltage, and a gate coupled to the first output terminal.
Claim 7
Dependent Claim
526 words
A full adder circuit implemented with an exclusive OR/NOR logic gate and having first and second input terminals for receiving first and second addends respectively, and a third input terminal for receiving a carry input bit, comprising: first inverter means having an input coupled to the first input terminal, and an output; second inverter means having an input coupled to the second input terminal, and an output; a first transistor of a first conductivity type having a first current electrode coupled to the output of the first inverter means, a second current electrode coupled to a first intermediate node, and a control electrode coupled to the second input terminal; a second transistor of the first conductivity type having a first current electrode coupled to the first input terminal, a second current electrode coupled to a second intermediate node, and a control electrode coupled to the second input terminal; a third transistor of the first conductivity type having a first current electrode coupled to the first output terminal, a second current electrode coupled to the first intermediate node, and a control electrode coupled to the output of the second inverter means; a fourth transistor of the first conductivity type having a first current electrode coupled to the output of the first inverter means, a second current electrode coupled to the second intermediate node, and a control electrode coupled to the output of the second inverter means; a pair of transistors of a second conductivity type, each transistor of the pair having first and second current electrodes coupled between a predetermined one of the first or second intermediate nodes and a power supply terminal, and the pair of transistors having the gates thereof cross-coupled, each gate being coupled to a predetermined one of the second or first intermediate nodes, respectively; third inverter means having an input coupled to a carry input terminal for receiving the carry input bit, and an output; first switching means having a first terminal coupled to the output of the second inverter means, a first control terminal coupled to the first intermediate node, a second control terminal coupled to the second intermediate node, and a second terminal; second switching means having a first terminal coupled to the output of the third inverter means, a second terminal coupled to the second terminal of the first switching means for providing an inverted carry output signal, a first control terminal coupled to the second intermediate node, and a second control terminal coupled to the first intermediate node; third switching means having a first terminal coupled to the output of the third inverter means, a second terminal coupled to the second terminal of the third switching means, a first control terminal coupled to the first intermediate node, and a second control terminal coupled to the second intermediate node; and fourth switching means having a first terminal coupled to the output of the third inverter means, a second terminal coupled to the second terminal of the third switching means for providing a complement of the output sum bit, a first control terminal coupled to the first intermediate node, and a second control terminal coupled to the second intermediate node.
Claim 8
Dependent Claim
526 words
A full adder circuit implemented with an exclusive OR/NOR logic gate and having first and second input terminals for receiving first and second addends respectively, and a third input terminal for receiving a carry input bit, comprising: first inverter means having an input coupled to the first input terminal, and an output; second inverter means having an input coupled to the second input terminal, and an output; a first transistor of a first conductivity type having a first current electrode coupled to the output of the first inverter means, a second current electrode coupled to a first intermediate node, and a control electrode coupled to the second input terminal; a second transistor of the first conductivity type having a first current electrode coupled to the first input terminal, a second current electrode coupled to a second intermediate node, and a control electrode coupled to the second input terminal; a third transistor of the first conductivity type having a first current electrode coupled to the first output terminal, a second current electrode coupled to the first intermediate node, and a control electrode coupled to the output of the second inverter means; a fourth transistor of the first conductivity type having a first current electrode coupled to the output of the first inverter means, a second current electrode coupled to the second intermediate node, and a control electrode coupled to the output of the second inverter means; a pair of transistors of a second conductivity type, each transistor of the pair having first and second current electrodes coupled between a predetermined one of the first or second intermediate nodes and a power supply terminal, and the pair of transistors having the gates thereof cross-coupled, each gate being coupled to a predetermined one of the second or first intermediate nodes, respectively; third inverter means having an input coupled to a carry input terminal for receiving the carry input bit, and an output; first switching means having a first terminal coupled to the output of the second inverter means, a first control terminal coupled to the first intermediate node, a second control terminal coupled to the second intermediate node, and a second terminal; second switching means having a first terminal coupled to the output of the third inverter means, a second terminal coupled to the second terminal of the first switching means for providing an inverted carry output signal, a first control terminal coupled to the second intermediate node, and a second control terminal coupled to the first intermediate node; third switching means having a first terminal coupled to the output of the third inverter means, a second terminal coupled to the second terminal of the third switching means, a first control terminal coupled to the first intermediate node, and a second control terminal coupled to the second intermediate node; and fourth switching means having a first terminal coupled to the output of the third inverter means, a second terminal coupled to the second terminal of the third switching means for providing a complement of the output sum bit, a first control terminal coupled to the first intermediate node, and a second control terminal coupled to the second intermediate node.
Claim 9
Dependent Claim
42 words
The full adder circuit of claim 4, further comprising: fourth inverter means having an input coupled to the second terminals of the third and fourth switching means, and an output for providing an output sum bit of the first and second addends.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-12-14 | 1991-06-15 | 1991-12-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-12-14 | 1995-06-15 | 1995-12-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-12-14 | 1999-06-15 | 1999-12-15 | $7700.00 | Window Closed / Lapsed |