Logic circuit arrangement with field effect transistors matched thereto

Claim 1

A logic circuit arrangement suitable for short switching times, for large-scale integration with high component density, and for operation with a power supply with only one polarity of a supply voltage, comprising: a stage having a field effect transistor whose drain is direct coupled to a gate of a field effect transistor of a following stage; the field effect transistors each having an active semiconductor zone, source region, drain region, channel region, gate electrode, and gate insulation; at least one of the transistors having a source, drain, and channel region all of the same conductivity type and which would result in a normally on depletion type transistor but for a buried and charged electrode layer positioned within the gate insulation and buried under the gate electrode; a first insulating layer portion of the gate insulation separating said gate electrode and said electrode layer from one another, and a second insulating layer portion of the gate insulation separating the active semiconductor zone and said electrode layer from one another, the first and second layers having respective thicknesses d i ' and d i -d i ' such that they cannot be tunnelled through by charge carriers during normal operation of the circuit arrangement; a respective insulsting protective lateral spacing between the source and the buried electrode layer, and between the drain and the buried electrode layer, being substantially greater than the thicknesses d i ' and d i -d i ' and chosen so that non-aligned portions in the active semiconductor zone laterally of a vertically aligned portion of the active semiconductor zone beneath the gate electrode are substantially undepleted by the buried electrode layer so as to remain normally on; and the buried elecrode layer having an area-specific electrical charge Q HSS of Q HSS which is from 1 to 1.2 times ##EQU4## where ε h is a dielectric constant of the semiconductor material of the active zone, ε i is a dielectric constant of the gate insulation, d h is a thickness of the active semiconductor zone, N D is a doping of the active semiconductor zone with donors for n-conductive transistors, and Ψ mh is a work function difference of electrons (in volts) between a metal of the gate electrode and a material of the active semiconductor zone, said electrical charge having a magnitude which defines a transition from inhibiting and normally off with no voltage applied to the gate electrode to conductive operation of the transistor with voltage applied to the gate electrode which undepletes the vertically aligned portion.