Non-selective implantation process for forming contact regions in integrated circuits

Claim 1

In a process for fabricating an integrated circuit in a substrate containing both PMOS and NMOS devices, wherein process steps have been completed for forming in said substrate n-doped source and drain regions and p-doped source and drain regions, wherein the source and drain regions of one of said conductivity types is shallower than the source and drain regions of the opposite conductivity type, and wherein the process steps for forming electrical contacts to said source and drain regions have been completed up to the opening of contacts to said regions through an overlying insulating layer, a method for deepening the shallower source and drain regions of said one conductivity type to inhibit spiking of a subsequently formed metal contact thereon through said regions which comprises: introducing impurities of said one conductivity type into said substrate through said contact openings in said insulation layer in a dosage having a range sufficiently high to deepen said shallow source and drain regions of said one conductivity type yet not high enough to lower the breakdown voltage of the source and drain regions of said opposite conductivity type, whereby spiking from a subsequently formed metal contact through said initially shallow source and drain regions is inhibited without lowering the breakdown voltage of said source and drain regions of the opposite conductivity type without the need for masking the source and drain regions of said opposite conductivity type during said introduction of impurities.