Patent US4708770A successfully refreshed from Google Patents.
US4708770A
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Planarized process for forming vias in silicon wafers
Assignee: LSI Corp
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Filing: 1986-06-19
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Granted: 1987-11-24
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Expires: 2006-06-19
Abstract
Abstract A process for forming vias in semiconductor structures includes the step of forming a pillar on an underlying dielectric layer prior to deposition of the metallization layer. The pillar is located above the diffusion region preferably and serves to provide substantially equal distances or heights for etching vias from the top planarized surface to the metallization layer deposited over the field oxide region and over the diffusion region.
Inventors
- 👤 Nicholas F. Pasch
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 16:03
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/071; H10W20/081; H10P; H10P14/00; H10P14/60; H10P14/69; H10P14/692; H10P14/6921; H10P14/69215; H10P14/6922; H10P14/6923; H10P14/694; H10P14/6943; H10P14/69433; H10W20/092
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
143 words
A process for forming vias in a silicon wafer comprising the steps of: forming a field oxide region on a substrate; forming a diffusion region adjacent to said field oxide region on said substrate wherein said field oxide region is at a height different from said diffusion region; depositing dielectric material extending over said oxide and diffusion regions; configuring a pillar from a portion of said dielectric material at a first via location so that the top surface of said pillar is substantially at the same height as the top surface of said dielectric material at a second via location and a layer of said dielectric material remains over said field oxide and diffusion regions; depositing a metallization layer over said dielectric material including said pillar; coating said metallization layer with a planarized dielectric; and etching vias at said first and second locations.
Claim 2
Dependent Claim
143 words
A process for forming vias in a silicon wafer comprising the steps of: forming a field oxide region on a substrate; forming a diffusion region adjacent to said field oxide region on said substrate wherein said field oxide region is at a height different from said diffusion region; depositing dielectric material extending over said oxide and diffusion regions; configuring a pillar from a portion of said dielectric material at a first via location so that the top surface of said pillar is substantially at the same height as the top surface of said dielectric material at a second via location and a layer of said dielectric material remains over said field oxide and diffusion regions; depositing a metallization layer over said dielectric material including said pillar; coating said metallization layer with a planarized dielectric; and etching vias at said first and second locations.
Claim 3
Dependent Claim
34 words
A process for forming vias in a silicon wafer as in claim 1, wherein said first via location is above said diffusion region and said second via location is above said field oxide region.
Claim 4
Dependent Claim
24 words
A process for forming vias in a silicon wafer as in claim 1, wherein said deposited dielectric material comprises separate layers of different materials.
Claim 5
Dependent Claim
29 words
A process for forming vias in a silicon wafer as in claim 3, wherein said different materials comprise a layer of silicon dioxide and a layer of silicon nitride.
Claim 6
Dependent Claim
31 words
A process for forming vias in a silicon wafer as in claim 4, wherein said silicon dioxide is about 500 Å thick and said silicon nitride is about 1200 Å thick.
Claim 7
Dependent Claim
29 words
A process for forming vias in a silicon wafer as in claim 1, wherein said dielectric material comprises two layers of silicon dioxide, each having a different doping concentration.
Claim 8
Dependent Claim
25 words
A process for forming vias in a silicon wafer as in claim 1, wherein said dielectric material is a glass doped with boron and phosphorous.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-11-23 | 1991-05-25 | 1991-11-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-11-23 | 1995-05-25 | 1995-11-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-11-23 | 1999-05-25 | 1999-11-24 | $7700.00 | Window Closed / Lapsed |