Patent US4704547A successfully refreshed from Google Patents.
US4704547A
Expired / Lapsed
US
⏱️ 0.0 years remaining
IGFET gating circuit having reduced electric field degradation
Assignee: Nokia Bell Labs
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Filing: 1987-02-25
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Granted: 1987-11-03
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Expires: 2007-02-25
Abstract
Abstract As integrated field effect devices are scaled to smaller dimensions, the electric field in the channel increases for a constant operating voltage. This induces "hot electron" effects that reduce device reliability. The present invention reduces the voltage (and hence electric field) across one or more transistors in various complementary (e.g. CMOS) logic circuits. This is achieved while still obtaining a full logic swing (e.g., 0-5 volts) at the output of the logic. The technique also allows the retention of previous voltage levels (e.g., 5 volts) for operation of other portions of the integrated circuit (e.g., dynamic memory cells).
Inventors
- 👤 Howard C. Kirsch
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 12:35
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/003; H03K19/00346; H03K19/00361; H03K19/00315
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
164 words
An integrated circuit comprising first and second terminals for connection to a power supply voltage, a first field effect transistor of a first conductivity type, and a second field effect transistor of a second conductivity type opposite to said first conductivity type, with the gates of said transistors being coupled to a common input node, and with the source of said first transistor being connected to a first voltage node, and with the source of said second transistor being connected to a second voltage node, characterized in that said integrated circuit further comprises a protective transistor of said second conductivity type, wherein said protective transistor has its drain connected to the output node of said logic circuit, and its source connected in the drain current path of said second transistor, and its gate connected to means for supplying a regulated DC protective voltage, wherein said regulated voltage remains relatively constant as compared to changes in said power supply voltage over an expected operating range.
Claim 2
Dependent Claim
164 words
An integrated circuit comprising first and second terminals for connection to a power supply voltage, a first field effect transistor of a first conductivity type, and a second field effect transistor of a second conductivity type opposite to said first conductivity type, with the gates of said transistors being coupled to a common input node, and with the source of said first transistor being connected to a first voltage node, and with the source of said second transistor being connected to a second voltage node, characterized in that said integrated circuit further comprises a protective transistor of said second conductivity type, wherein said protective transistor has its drain connected to the output node of said logic circuit, and its source connected in the drain current path of said second transistor, and its gate connected to means for supplying a regulated DC protective voltage, wherein said regulated voltage remains relatively constant as compared to changes in said power supply voltage over an expected operating range.
Claim 3
Dependent Claim
15 words
The integrated circuit of claim 1 wherein said transistors are insulated gate field effect transistors.
Claim 4
Dependent Claim
39 words
The integrated cricuit of claim 2 wherein the gate electrodes of said transistors are insulated from the channels of said transistors by an insulator comprising silicon dioxide, and wherein the channels of said transistors are essentially comprised of silicon.
Claim 5
Dependent Claim
15 words
The integrated circuit of claim 1 wherein said power supply voltage is nominally 5 volts.
Claim 6
Dependent Claim
21 words
The integrated circuit of claim 1 wherein the expected operating range of the power supply voltage is 4.5 to 5.5 volts.
Claim 7
Dependent Claim
28 words
The integrated circuit of claim 1 wherein said first voltage node is connected to said first terminal, and said second voltage node is connected to said second terminal.
Claim 8
Dependent Claim
33 words
The integrated circuit of claim 1 wherein said first voltage node is connected to means for boosting the voltage on said first voltage node in excess of the voltage on said first terminal.
Claim 9
Dependent Claim
16 words
The integrated circuit of claim 1 further comprising an array of dynamic random access memory cells.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-11-02 | 1991-05-04 | 1991-11-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-11-02 | 1995-05-04 | 1995-11-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-11-02 | 1999-05-04 | 1999-11-03 | $7700.00 | Window Closed / Lapsed |