CMOS Schmitt trigger

Claim 2

A Schmitt trigger comprising: a first p-channel MOSFET (T2) whose drain is connected to a ground rail and a first n-channel MOSFET (T1) whose drain is connected to a voltage supply rail positive with respect to said ground rail, whose gates are connected to a common input, and whose sources are connected together, said first p-channel MOSFET and said first n-channel MOSFET forming a non-inverting configuration; a second p-channel MOSFET (T3) whose source is connected to said voltage supply rail, and whose gate is connected to the source of said first p-channel MOSFET (T2), and a second n-channel MOSFET (T4) whose source is connected to the ground rail, whose gate is connected to the gate of the second p-channel MOSFET (T3) and whose drain is connected to the drain of the second p-channel MOSFET (T3) to form a common output, said second p-channel MOSFET and said second n-channel MOSFET forming an inverting configuration; a third p-channel MOSFET (T5) whose source is connected to said voltage supply rail, whose drain is connected to the gate of the second p-channel MOSFET (T3) and whose gate is connected to the drain of the second p-channel MOSFET (T3); and a third n-channel MOSFET (T6) whose source is connected to said ground rail, whose drain is connected to the gate of the second n-channel MOSFET (T4) and whose gate is connected to the drain of the second n-channel MOSFET (T4).

Claim 3

A Schmitt trigger circuit as in claim 1 wherein said MOSFETs T1-T6 have channel widths approximately of the following relative values: T1=120, T2=175, T3=125, T4=80, T5=5 and T6=5.

Claim 4

A CMOS Schmitt trigger circuit consisting essentially of only six MOS field effect transistor (FETs) interconnected to accept a varying input electrical signal and to produce on a common output line a bi-level output electrical signal, which output signal switches from a first to a second level in response to said input signal increasing through a first switching point value, and which output signal switches from said second level to said first level in response to said input signal decreasing through a second switching point value, a common input for receiving said input signal, a first complementary pair of MOSFETs connected in a non-inverting configuration, each having a gate connected to receive said input signal and their respective source-drain paths connected between a pair of voltage supply lines and to an intermediate bus line, a second complementary pair of MOSFETs connected in an inverting configuration, each having a gate connected to said intermediate bus line and respective source-drain paths connected between a pair of voltage supply lines and to a common output line, for outputting said bi-level output signal, a fifth FET having a gate connected to said common output line and having a source-drain path connected to said intermediate bus line, to the gates of the second pair of FETs and across a first one of said second pair of FETs for maintaining a stable output signals until said first switching point value is reached, after which said fifth FET assists in achieving a rapid change in said output signal; and a sixth FET having a gate connected to said common output line and having a source-drain path connected to said intermediate bus line, to the gates of the second pair of FETs and across a second one of said second pair of FETs for maintaining a stable output signal until said second switching point value is reached, after which said sixth FET assists in achieving a rapid change in said output signal whereby said first and second switching point values are determined by the relative dimensions of the channels of one of said fifth and sixth MOSFETs and one of said complementary MOSFETs.

Claim 5

A CMOS Schmitt trigger circuit consisting essentially of only six MOS field effect transistor (FETs) interconnected to accept a varying input electrical signal and to produce on a common output line a bi-level output electrical signal, which output signal switches from a first to a second level in response to said input signal increasing through a first switching point value, and which output signal switches from said second level to said first level in response to said input signal decreasing through a second switching point value, a common input for receiving said input signal, a first complementary pair of MOSFETs connected in a non-inverting configuration, each having a gate connected to receive said input signal and their respective source-drain paths connected between a pair of voltage supply lines and to an intermediate bus line, a second complementary pair of MOSFETs connected in an inverting configuration, each having a gate connected to said intermediate bus line and respective source-drain paths connected between a pair of voltage supply lines and to a common output line, for outputting said bi-level output signal, a fifth FET having a gate connected to said common output line and having a source-drain path connected to said intermediate bus line, to the gates of the second pair of FETs and across a first one of said second pair of FETs for maintaining a stable output signals until said first switching point value is reached, after which said fifth FET assists in achieving a rapid change in said output signal; and a sixth FET having a gate connected to said common output line and having a source-drain path connected to said intermediate bus line, to the gates of the second pair of FETs and across a second one of said second pair of FETs for maintaining a stable output signal until said second switching point value is reached, after which said sixth FET assists in achieving a rapid change in said output signal whereby said first and second switching point values are determined by the relative dimensions of the channels of one of said fifth and sixth MOSFETs and one of said complementary MOSFETs.

Claim 6

A Schmitt trigger circuit comprising: a first pair of MOSFETs T1 and T2 connected in a non-inverting configuration having gates connected to a common input line A and having their respective source-drain paths connected between a pair of voltage supply lines and to an intermediate bus line B; a second pair of MOSFETs T3 and T4 connected in an inverting configuration having gates connected to said intermediate bus line B and having their respective source-drain paths connected between said pair of voltage supply lines and to a common output line C; a fifth MOSFET T5 having a gate connected to said common output line C and having a source-drain path connected between a first one of said voltage supply lines and the gate of T3, said source-drain path of said fifth MOSFET being further connected to said intermediate bus line B; and a sixth MOSFET T6 having a gate connected to said common output line C and having a source-drain path connected between the other one of said voltage supply lines and the gate of T4, said source-drain path of said sixth MOSFET being further connected to said intermediate bus line B.

Claim 7

A Schmitt trigger circuit comprising: a first pair of MOSFETs T1 and T2 connected in a non-inverting configuration having gates connected to a common input line A and having their respective source-drain paths connected between a pair of voltage supply lines and to an intermediate bus line B; a second pair of MOSFETs T3 and T4 connected in an inverting configuration having gates connected to said intermediate bus line B and having their respective source-drain paths connected between said pair of voltage supply lines and to a common output line C; a fifth MOSFET T5 having a gate connected to said common output line C and having a source-drain path connected between a first one of said voltage supply lines and the gate of T3, said source-drain path of said fifth MOSFET being further connected to said intermediate bus line B; and a sixth MOSFET T6 having a gate connected to said common output line C and having a source-drain path connected between the other one of said voltage supply lines and the gate of T4, said source-drain path of said sixth MOSFET being further connected to said intermediate bus line B.

Claim 8

A Schmitt trigger circuit as in claim 4 wherein the relative channel dimensions of T6 and T1 determine a first switching point value whereat an increasing input voltage on input line A passing through said first switching point value causes an abrupt change in output voltage on line C from a first output value to a second output value, and wherein the relative channel dimensions of T5 and T2 determine a second switching point value whereat a decreasing input voltage on input line A passing through said second switching point value causes an abrupt change in output voltage on line C from said second output value to said first output value.

Claim 9

A Schmitt trigger circuit as in claim 5 wherein said MOSFETs T1-T6 have channel width sizes approximately of the following relative values: T1=120, T2=175, T3=125, T4=80, T5=5 and T6=5.