TTL-ECL level converter operable with small time delay by controlling saturation

Claim 1

A signal level converter comprising: a positive power supply line; a grounding line; a negative power supply line; an input terminal receiving an input signal, said input signal having low and high logic levels; an input diode connected to said input terminal at a cathode and having an anode; an input transistor having a collector connected to said positive power supply line, a base connected to said anode of said input diode and an emitter; a first series connection of diodes between said anode of said input diode and said grounding line, said diodes in said first series connection being forward-biased when said input signal is at said high logic level; a second series connection of diodes coupled at one end to said emitter of said input transistor and having an other end; a current source connected between said other end of said second series connection and said grounding line, said diodes in said second series connection being forward-biased when said input signal is at said high logic level; a voltage source generating a reference voltage; a clamping transistor having a collector connected to said grounding line, a base receiving said reference voltage and an emitter connected to said other end of said second series connection; and a comparing means for comparing a voltage at said other end of said second series connection with said reference voltage, said comparing means being energized by a power voltage between said negative power supply line and said grounding line, and producing an output signal as a result of comparison.