Voltage-temperature compensated threshold for hysteresis line receiver at TTL supply voltage

Claim 2

A line receiver circuit having an input hysteresis characteristic which is compensated for both temperature changes and variations in supply voltage with a single transistor-transistor logic compatible power supply, said receiver circuit comprising: a receiver circuit portion including a first reference transistor and a second reference transistor, said first reference transistor having its base connected to an input circuit terminal for receiving a logic signal, its collector coupled to a supply voltage potential via a Schottky diode and its emitter coupled to the emitter of said second reference transistor, said second reference transistor having its base connected to a threshold voltage node and its collector connected to the voltage potential via a load resistor; said receiver circuit portion further including a multi-emitter output transistor having first and second emitters, said output transistor having its base connected to the collector of said second reference transistor, its collector to the voltage potential and its first emitter connected to an output circuit terminal; a first voltage divider network formed of a first resistor and a second resistor, one end of the first resistor being connected to one end of the second resistor and to the threshold voltage node, the other end of the first resistor being connected to receive a constant reference voltage, the other end of the second resistor being connected to a ground potential; a second voltage divider network formed of the first resistor and a third resistor, one end of the third resistor being connected to the common connection of the first and second resistors and threshold voltage node; and a feedback switching transistor having its base coupled to the second emitter of said output transistor, its collector connected to the other end of the third resistor and its emitter connected to the ground potential.

Claim 3

A line receiver circuit as claimed in claim 1, further comprising a first current source connected to the common emitters of said first and second reference transistors.

Claim 4

A line receiver circuit as claimed in claim 2, wherein said first current source is formed of a transistor and a resistor.

Claim 5

A line receiver circuit as claimed in claim 3, further comprising a second current source coupled to the second emitter of said output transistor via a resistor.

Claim 6

A line receiver circuit as claimed in claim 4, wherein said second current source is formed of a transistor and a resistor.

Claim 7

A line receiver circuit as claimed in claim 1, wherein said switching transistor is turned off to generate a high threshold voltage at the threshold voltage node via the first voltage divider network when the input logic signal is in the low level state.

Claim 8

A line receiver circuit as claimed in claim 1, wherein said switching transistor is turned on to generate a low level threshold voltage at the threshold voltage node via the second voltage divider network when the input logic signal is in the high level state.

Claim 9

A line receiver circuit as claimed in claim 1, wherein said constant reference voltage is provided by a bandgap circuit portion.

Claim 10

A line receiver circuit as claimed in claim 1, wherein said line receiver circuit is formed as an integrated circuit on a single semiconductor chip.

Claim 11

A line receiver circuit having an input hysteresis characteristic which is compensated for both temperature changes and variations in supply voltage with a single transistor-transistor logic compatible power supply, said receiver circuit comprising: a receiver circuit portion including a first reference transistor and a second reference transistor, said first reference transistor having its base connected to an input circuit terminal for receiving a logic signal, its collector coupled to a supply voltage potential via a Schottky diode and its emitter coupled to the emitter of said second reference transistor, said second reference transistor having its base connected to a threshold voltage node and its collector connected to the voltage potential via a load resistor; said receiver circuit portion further including a multi-emitter output transistor having first and second emitters, said output transistor having its base connected to the collector of said second reference transistor, its collector connected to the voltage potential and its first emitter connected to an output circuit terminal; a bandgap circuit portion for generating a constant reference voltage; a first voltage divider network formed of a first resistor and a second resistor, one end of the first resistor being connected to one end of the second transistor and to the threshold voltage node, the other end of the first resistor being connected to receive the constant reference voltage, the other end of the second resistor being connected to a ground potential; a second voltage divider network formed of the first resistor and a third resistor, one end of the third resistor being connected to the common connection of the first and second resistors and threshold voltage node; and a feedback switching transistor having its base coupled to the second emitter of said output transistor via a resistor and diode, its collector connected to the other end of the third resistor and its emitter connected to the ground potential.

Claim 12

A line receiver circuit having an input hysteresis characteristic which is compensated for both temperature changes and variations in supply voltage with a single transistor-transistor logic compatible power supply, said receiver circuit comprising: a receiver circuit portion including a first reference transistor and a second reference transistor, said first reference transistor having its base connected to an input circuit terminal for receiving a logic signal, its collector coupled to a supply voltage potential via a Schottky diode and its emitter coupled to the emitter of said second reference transistor, said second reference transistor having its base connected to a threshold voltage node and its collector connected to the voltage potential via a load resistor; said receiver circuit portion further including a multi-emitter output transistor having first and second emitters, said output transistor having its base connected to the collector of said second reference transistor, its collector connected to the voltage potential and its first emitter connected to an output circuit terminal; a bandgap circuit portion for generating a constant reference voltage; a first voltage divider network formed of a first resistor and a second resistor, one end of the first resistor being connected to one end of the second transistor and to the threshold voltage node, the other end of the first resistor being connected to receive the constant reference voltage, the other end of the second resistor being connected to a ground potential; a second voltage divider network formed of the first resistor and a third resistor, one end of the third resistor being connected to the common connection of the first and second resistors and threshold voltage node; and a feedback switching transistor having its base coupled to the second emitter of said output transistor via a resistor and diode, its collector connected to the other end of the third resistor and its emitter connected to the ground potential.

Claim 13

A line receiver circuit as claimed in claim 10, further comprising a first current source connected to the common emitters of said first and second reference transistors.

Claim 14

A line receiver circuit as claimed in claim 11, wherein said first current source is formed of a transistor and a resistor.

Claim 15

A line receiver circuit as claimed in claim 12, further comprising a second current source coupled to the second emitter of said output transistor via a resistor.

Claim 16

A line receiver circuit as claimed in claim 13, wherein said second current source is formed of a transistor and a resistor.

Claim 17

A line receiver circuit as claimed in claim 10, wherein said switching transistor is turned off to generate a high threshold voltage at the threshold voltage node via the first voltage divider network when the input logic signal is in the low level state.

Claim 18

A line receiver circuit as claimed in claim 10, wherein said switching transistor is turned on to generate a low level threshold voltage at the threshold voltage node via the second voltage divider network when the input logic signal is in the high level state.

Claim 19

A line receiver circuit as claimed in claim 10, wherein said line receiver circuit is formed as an integrated circuit on a single semiconductor chip.