ECL Circuit having a negative feedback differential transistor circuit to increase the operating speed of the output circuit

Claim 2

A semiconductor integrated circuit device comprising: an input terminal for receiving an input signal having a high voltage level and a low voltage level; an input circuit including a first transistor having its base coupled to said input terminal to receive said input signal through said input terminal and its collector coupled to a first power source terminal, a second transistor having an emitter coupled to an emitter of said first transistor to perform current switching operations with said first transistor, a load element connected between the collector of sid second transistor and the first power source terminal, a current source element connected between the emitters of said first and second transistors and a second power source terminal, a bias circuit coupled to receive a collector output of said second transistor including means for generating a bias voltage to be fed to the base of said second transistor, and an output terminal coupled to the collector of said second transistor, wherein said load element and said bias circuit have circuit parameters which are set so that said input circuit generates an output signal at said output terminal which has a high voltage level substantially equal to the high voltage level of said input signal and a low voltage level higher than the low voltage level of said input signal; and an ECL circuit coupled between the first power source terminal and the second power source terminal for receiving said output signal from said output terminal of said input circuit.

Claim 3

A semiconductor integrated circuit device according to claim 1, wherein said ECL circuit includes: a third transistor having a collector coupled to the first power source terminal, an emitter and a base, said base being coupled to the output terminal of the input circuit to be fed with said output signal from said input circuit; a fourth transistor having a collector coupled to the first power source terminal, an emitter coupled to the emitter of said third transistor, and a base coupled to a threshold voltage source to be fed with a threshold voltage which is at a higher level than a threshold voltage necessary for recognizing the high and low levels of the input signal fed to said input terminal; and a current source element connected between the emitters of said first and second transistors and the second power source terminal.

Claim 4

A semiconductor integrated circuit device according to claim 2, wherein said bias circuit has a level shift element connected between the collector and base of said second transistor.

Claim 5

A semiconductor integrated circuit device according to claim 2, wherein said bias circuit further includes an emitter follower transistor having a base coupled to the collector of said second transistor, an emitter coupled to the base of said second transistor, and a collector coupled to the first power source terminal, and wherein said bias circuit is constructed of a level shift circuit coupled to receive the emitter output of said emitter follower transistor for generating a voltage to be fed to the base of said second transistor.

Claim 6

A semiconductor integrated circuit device according to claim 4, wherein said level shift circuit has a first resistance element connected between the emitter of said emitter follower transistor and the base of said second transistor, and a second resistance element connected between the base of said second transistor and a third power source terminal and wherein said output terminal is coupled between the emitter of said follower transistor and said first resistance element.

Claim 7

A semiconductor integrated circuit device according to claim 4, wherein a collector load resistance element is connected between the collector of said first transistor and the first power source terminal.

Claim 8

A semiconductor integrated circuit device according to claim 1, further comprising: an output circuit coupled to receive an output signal of said ECL circuit and including means for generating an output signal which has high and low voltage levels corresponding to the high and low voltage levels of said input signal applied to said input terminal, respectively; and an output terminal coupled to be fed with the output signal of said output circuit.

Claim 9

A semiconductor integrated circuit device according to claim 7, wherein said output circuit includes a fifth transistor for current switching operations, a level shift element coupled to the collector of said fifth transistor, a collector load resistance element coupled between said level shift element and said first power source terminal, and an emitter follower transistor having a base coupled to a common connection between said collector load resistance and said level shift element, a collector coupled to said first power source terminal and an emitter coupled to said second power source terminal through an emitter resistance, whereby a signal which has high and low voltage levels corresponding to the high and low voltage levels of said output signal of said input circuit is generated from said emitter.

Claim 10

A semiconductor integrated circuit device according to claim 8, wherein the level shift element of said output circuit is made of a resistance element.

Claim 11

A semiconductor integrated circuit device according to claim 9, wherein said output circuit further includes: an emitter follower transistor having a base coupled to the collector of said fifth transistor and an emitter coupled to an output terminal.

Claim 12

A semiconductor integrated circuit device comprising: an input terminal; an ECL circuit coupled to said input terminal including means coupled between a first power source terminal and a second power source terminal for generating an output signal having high and low voltage levels corresponding to the high and low voltage levels of an input signal fed to said input terminal; an output circuit coupled to receive said ECL output signal including a first current switch transistor to be controlled by the output signal of said ECL circuit, a level shift element coupled to the collector of said current switch transistor, and a resistance element connected between said level shift element and the first power source terminal, wherein said output circuit generates an output signal which has a high voltage level made substantially equal to the high voltage level of the output signal of said ECL circuit and a low voltage level made lower than the low voltage level of the output signal of said ECL circuit; and an output terminal coupled to be fed with an output signal which is generated at the common connection between the collector of said first current switch transistor and said level shift element.

Claim 13

A semiconductor integrated circuit device comprising: an input terminal; an ECL circuit coupled to said input terminal including means coupled between a first power source terminal and a second power source terminal for generating an output signal having high and low voltage levels corresponding to the high and low voltage levels of an input signal fed to said input terminal; an output circuit coupled to receive said ECL output signal including a first current switch transistor to be controlled by the output signal of said ECL circuit, a level shift element coupled to the collector of said current switch transistor, and a resistance element connected between said level shift element and the first power source terminal, wherein said output circuit generates an output signal which has a high voltage level made substantially equal to the high voltage level of the output signal of said ECL circuit and a low voltage level made lower than the low voltage level of the output signal of said ECL circuit; and an output terminal coupled to be fed with an output signal which is generated at the common connection between the collector of said first current switch transistor and said level shift element.

Claim 14

A semiconductor ECL integrated circuit device comprising: an input terminal coupled to receive an input signal from an outside ECL circuit, said input signal having a high voltage level and a low voltage level; an input circuit coupled to said input terminal including means for converting said input signal into a first minor amplitude ECL signal having an amplitude smaller than that of said input signal, said input circuit comprising a first transistor having its base fed with said input signal through said input terminal and its collector coupled to a first power source terminal, a second transistor having an emitter coupled to the emitter of said first transistor to perform current switching operations with said first transistor, a load element connected between the collector of said second transistor and the first power source terminal, a current source element connected between the emitters of said first and second transistors and a second power source terminal, a negative feedback bias circuit coupled to receive the collector output of said second transistor, said bias circuit including means for generating a bias voltage corresponding to the collector voltage of said second transistor to be fed to the base of said second transistor, and an output terminal coupled to the collector of said second transistor, wherein said load element and said bias circuit have circuit parameters which are set so that said input circuit generates said first minor amplitude ECL signal at said output terminal which has a high voltage level substantially equal to the high voltage level of said input signal and a low voltage level higher than the low voltage level of said input signal, and so that the difference between the collector output voltage V CO of the second transistor and a base feedback voltage V F1 to the base of the second transistor remains substantially constant; an ECL circuit coupled to said output terminal of said input circuit for receiving said first minor amplitude ECL output signal and coupled between the first and the second power source terminal, said ECL circuit including means for operating in response to said first minor amplitude output signal from said input circuit to produce a second minor amplitude ECL output signal having high and low voltage levels corresponding to the high and low voltage levels of the first minor amplitude output signal of said input circuit.

Claim 15

A semiconductor ECL integrated circuit device comprising: an input terminal coupled to receive an input signal from an outside ECL circuit, said input signal having a high voltage level and a low voltage level; an input circuit coupled to said input terminal including means for converting said input signal into a first minor amplitude ECL signal having an amplitude smaller than that of said input signal, said input circuit comprising a first transistor having its base fed with said input signal through said input terminal and its collector coupled to a first power source terminal, a second transistor having an emitter coupled to the emitter of said first transistor to perform current switching operations with said first transistor, a load element connected between the collector of said second transistor and the first power source terminal, a current source element connected between the emitters of said first and second transistors and a second power source terminal, a negative feedback bias circuit coupled to receive the collector output of said second transistor, said bias circuit including means for generating a bias voltage corresponding to the collector voltage of said second transistor to be fed to the base of said second transistor, and an output terminal coupled to the collector of said second transistor, wherein said load element and said bias circuit have circuit parameters which are set so that said input circuit generates said first minor amplitude ECL signal at said output terminal which has a high voltage level substantially equal to the high voltage level of said input signal and a low voltage level higher than the low voltage level of said input signal, and so that the difference between the collector output voltage V CO of the second transistor and a base feedback voltage V F1 to the base of the second transistor remains substantially constant; an ECL circuit coupled to said output terminal of said input circuit for receiving said first minor amplitude ECL output signal and coupled between the first and the second power source terminal, said ECL circuit including means for operating in response to said first minor amplitude output signal from said input circuit to produce a second minor amplitude ECL output signal having high and low voltage levels corresponding to the high and low voltage levels of the first minor amplitude output signal of said input circuit.

Claim 16

A semiconductor ECL integrated circuit device according to claim 12, wherein the negative feedback bias circuit comprises a negative feedback transistor and a pair of resistors coupled in series between an emitter of the negative feedback transistor and a third power source terminal, the base of said negative feedback transistor being coupled to the collector of the second transistor, the base of the second transistor being coupled to a junction between said pair of resistors, and the output terminal for the input circuit being coupled between the emitter of the negative feedback transistor and the pair of resistors.

Claim 17

A semiconductor ECL integrated circuit device according to claim 12, further comprising: an output circuit coupled to receive the second minor amplitude ECL output signal from the ECL circuit comprising: a third transistor having a base coupled to receive said second minor amplitude output signal from said ECL circuit; a load element coupled between the first power source terminal and a collector of said third transistor; a fourth transistor having an emitter coupled to an emitter of the third transistor to operate as a current switch in conjunction with the third transistor; a load element coupled between the first power source terminal and a collector of said fourth transistor; a current source element coupled between the emitters of said first and second transistors and the second power source terminal; and an output terminal coupled to the collector of said fourth transistor, wherein parameters of said load elements are set so that an output signal is produced at the output terminal of said output circuit having high and low levels equal to the high and low levels of an input signal applied to the input terminal of the ECL integrated circuit.

Claim 18

A semiconductor ECL integrated circuit device according to claim 14, further comprising: a fixed reference voltage source applied to a base of said fourth transistor; first and second resistors coupled in series to a collector of said third transistor; third and fourth resistors coupled in series to a collector of said fourth transistor; a first emitter follower transistor coupled to a junction of said first and second resistors, said first emitter follower transistor having an output terminal at its emitter; a second emitter follower transistor coupled to a junction of said third and fourth resistors, said second emitter follower transistor having an output terminal at its emitter; and a fifth transistor having a base coupled to a collector of said fourth transistor and an emitter coupled to the output terminal for said output circuit, wherein the values of the first, second, third and fourth resistors are set so that a third minor amplitude ECL signal is produced at the output of the first emitter follower transistor and a fourth minor amplitude ECL signal is produced at the output of said second emitter follower transistor.

Claim 19

A semiconductor ECL integrated circuit device according to claim 14, further comprising: a first resistor coupled to a collector of the third transistor; second and third resistors coupled in series to a collector of the fourth transistor; and a negative feedback bias circuit coupled between a junction of the second and third resistors in a base of the fourth transistor, said negative feedback bias circuit comprising a fifth transistor and fourth and fifth resistors, wherein a base of the fifth transistor is coupled to a junction between said second and third resistors, the fourth and fifth resistors are coupled in series between an emitter of said fifth transistor and a third power source terminal, and wherein a junction between the fourth and fifth resistors is coupled to the base of said fourth transistor.

Claim 20

A semiconductor ECL integrated circuit device according to claim 13, further comprising: an output circuit coupled to receive the second minor amlitude ECL output signal from the ECL circuit comprising: a third transistor having a base coupled to receive said second minor amplitude output signal from said ECL circuit; a load element connected between a collector of said third transistor and said first power source terminal; a fourth transistor having an emitter coupled to an emitter of the third transistor to operate as a current switch in conjunction with the third transistor; a load element connected between a collector of said fourth transistor and said first power source terminal; and an output terminal coupled to a collector of said fourth transistor, wherein parameters of said load elements are set so that an output signal is produced at the output terminal of said output circuit having high and low voltage levels corresponding to the high and low voltage levels of an input signal applied to the input terminal of the ECL integrated circuit.

Claim 21

A semiconductor ECL integrated circuit device according to claim 12, wherein said negative feedback bias circuit comprises: a negative feedback transistor having a base coupled to a collector of the second transistor; and an emitter resistor and a constant-current source coupled in series with an emitter of the negative feedback transistor, wherein a base of the second transistor is coupled to a junction between the resistor and the constant-current source, and wherein the output terminal for the input circuit is coupled between a junction of the emitter and emitter resistor.