An emitter-coupled logic circuit device
Abstract
Abstract The circuit device comprises first and second voltage supply lines (Li, L 2 ) connected to ground and an external voltage source (VEE) respectively, a voltage regulator (6) connected between the first (L 1 ) and the second (L 2 ) voltage supply lines and having an output terminal connected to a third voltage supply line (L 3 ) to provide the third voltage supply line (L 3 ) with a potential between that of the first (Li) and that of the second (L 2 ) voltage supply line, an output buffer circuit (3) connected between the first (Li) and the third (L 3 ) voltage supply lines, and an inner logic gate circuit (2) connected between the third (L 3 ) and the second (L 2 ) voltage supply lines, so that the current flowing through the output buffer circuit (3) also flows through the inner logic gate circuit (2).
Inventors
- 👤 Takeda Hirofumi
Bibliographic Details
Claims Analysis
Total Claims: 1References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.