Transistor-transistor logic to emitter coupled logic translator

Claim 2

An improved transistor-transistor logic (TTL) to emitter coupled logic (ECL) translator comprising: TTL input gate means for receiving TTL voltage level logic input signals in the positive voltage range compatible with TTL circuits; ECL output gate means for delivering corresponding ECL voltage level logic output signals in the negative voltage range compatible with ECL circuits, said ECL output gate comprising an input transistor and a reference transistor providing alternate input transistor and reference transistor collector current paths operatively coupled for switching current between the alternate current paths according to signals at the base of the input transistor; translating current source means operatively coupled between the TTL input gate means and the ECL output gate means for applying translated signals to the input transistor of the ECL output gate means in the negative voltage range according to the input signals at the TTL input gate means; and clamp means operatively coupled between the TTL input gate means and ECL output gate means for limiting the swing of said translated signals in the negative voltage range applied by the translating current source at the input transistor of the ECL output gate means thereby reducing propagation delay across the translator and reducing power dissipation.

Claim 3

The TTL to ECL translator of claim 1 wherein said clamp means comprises a bidirectional clamp.

Claim 4

The TTL to ECL translator of claim 2 wherein the bidirectional clamp comprises a clamp bridge, said bridge having an input node coupled to the TTL input gate means, an output node coupled to the ECL output gate means, a ground node coupled to ground potential, and a floating node.

Claim 5

The TTL to ECL translator of claim 3 wherein the input node of the clamp bridge is coupled to the output of the TTL input gate means, the output node of the clamp bridge is coupled to the base of the input transistor of the ECL output gate means, and the translating current source means is operatively coupled to the output node of the clamp bridge, said clamp bridge thereby limiting the voltage range of signals applied to the ECL input gate means by the translating current source means.

Claim 6

The TTL to ECL translator of claim 4 wherein the base of the reference transistor of the ECL output gate means is coupled through diode means to the ground node of the clamp bridge and wherein a reference current source is coupled to the base of said reference transistor for applying a reference voltage in the negative voltage range at the base of said reference transistor.

Claim 7

The TTL to ECL translator of claim 3 wherein said clamp bridge comprises first and second diode means coupled on either side of the floating node and first and second base collector shorted transistor means coupled on either side of the ground node.

Claim 8

The TTL to ECL translator of claim 3 wherein said clamp bridge comprises first and second diode junction means coupled on either side of the floating mode and third and fourth diode junction means coupled on either side of the ground node.

Claim 9

The TTL to ECL translator of claim 7 wherein the diode junction area of the third and fourth diode junction means is relatively smaller than the diode junction area of the first and second diode junction means so that the voltage drop across the first and second diode junction means is smaller than the voltage drop across the third and fourth diode junction means.

Claim 10

The TTL to ECL translator of claim 8 wherein the third and fourth diode junction means comprise base collector shorted transistors with base emitter junction areas relatively smaller than the diode junction areas of the first and second diode junction means.

Claim 11

An improved transistor-transistor logic (TTL) to emitter coupled logic (ECL) translator having input gate means for receiving TTL voltage level logic input signals in the positive voltage range compatible with TTL circuits, an ECL output gate means for delivering corresponding ECL voltage level logic output signals in the negative voltage range compatible with ECL circuits, said ECL output gate means comprising an input transistor and a reference transistor providing alternate collector current paths operatively coupled for switching current between the current paths according to signals at the base of the input transistor, and a translating current source operatively coupled between the input gate means and the ECL output gate means for applying translated signals in the negative voltage range to the base of the input transistor of the ECL output gate means according to the input signals at the input gate means, the improvement comprising: said input gate means comprising a TTL input gate; and clamp means operatively coupled between the TTL input gate means and the ECL output gate means for limiting the range of translated signals in the negative voltage range applied by the translating current source at the base of the input transistor of the ECL output gate means thereby reducing propagation delay across the translator and reducing power dissipation.

Claim 12

An improved transistor-transistor logic (TTL) to emitter coupled logic (ECL) translator having input gate means for receiving TTL voltage level logic input signals in the positive voltage range compatible with TTL circuits, an ECL output gate means for delivering corresponding ECL voltage level logic output signals in the negative voltage range compatible with ECL circuits, said ECL output gate means comprising an input transistor and a reference transistor providing alternate collector current paths operatively coupled for switching current between the current paths according to signals at the base of the input transistor, and a translating current source operatively coupled between the input gate means and the ECL output gate means for applying translated signals in the negative voltage range to the base of the input transistor of the ECL output gate means according to the input signals at the input gate means, the improvement comprising: said input gate means comprising a TTL input gate; and clamp means operatively coupled between the TTL input gate means and the ECL output gate means for limiting the range of translated signals in the negative voltage range applied by the translating current source at the base of the input transistor of the ECL output gate means thereby reducing propagation delay across the translator and reducing power dissipation.

Claim 13

The TTL to ECL translator of claim 10 wherein the clamp means comprises a bidirectional clamp bridge, said bridge having an input node coupled to the TTL input gate means, an output node coupled to the ECL output gate means, a ground node coupled to ground potential, and a floating node.

Claim 14

The TTL to ECL translator of claim 11 wherein the input node of the clamp bridge is coupled to the output of the TTL input gate means, wherein the output node of the clamp bridge is coupled to the base of the input transistor of the ECL output gate means, and wherein the translating current source is also coupled to the output node of the clamp bridge whereby translated signals applied to the base of said input transistor of the ECL output gate means are limited in voltage range by the clamp bridge.

Claim 15

The TTL to ECL translator of claim 12 wherein said bidirectional clamp bridge comprises first and second diode means coupled at either side of the floating node and third and fourth diode means coupled at either side of the ground node.

Claim 16

The TTL to ECL translator of claim 13 wherein the third and fourth diode means comprise base collector shorted transistors having base emitter junction areas smaller than the diode junction areas of the first and second diode means.

Claim 17

The TTL to ECL translator of claim 13 wherein the base of said reference transistor is coupled through reference diode means to said ground node and further comprising a reference current source for applying a reference voltage below ground potential at the base of said reference transistor.

Claim 18

An improved transistor-transistor logic (TTL) to emitter coupled logic (ECL) translator comprising: TTL input gate means for receiving TTL voltage level logic input signals in the positive voltage range compatible with TTL circuits; a translating current source operatively coupled between the output of the TTL input gate means and negative potential for generating translated ECL voltage level logic output signals compatible with ECL circuits corresponding to the input signals at the TTL input gate means; and clamp means operatively coupled between the TTL input gate means and translating current source for limiting the range of said translated signals in the negative voltage range thereby reducing propagation delay across the translator and reducing power dissipation.

Claim 19

An improved transistor-transistor logic (TTL) to emitter coupled logic (ECL) translator comprising: TTL input gate means for receiving TTL voltage level logic input signals in the positive voltage range compatible with TTL circuits; a translating current source operatively coupled between the output of the TTL input gate means and negative potential for generating translated ECL voltage level logic output signals compatible with ECL circuits corresponding to the input signals at the TTL input gate means; and clamp means operatively coupled between the TTL input gate means and translating current source for limiting the range of said translated signals in the negative voltage range thereby reducing propagation delay across the translator and reducing power dissipation.

Claim 20

The TTL to ECL translator of claim 16 wherein the clamp means comprises a bidirectional clamp bridge, said bridge having an input node coupled to the output of the TTL input gate means, an output node coupled to the translating current source, a ground node coupled to ground potential and a floating node.

Claim 21

The TTL to ECL translator of claim 17 wherein said clamp bridge comprises first and second diode means coupled on either side of the floating node and third and fourth diode means coupled on either side of said ground node and wherein the diode junction area of the third and fourth diode means is smaller than the junction area of the first and second diode means for establishing translating signals in the negative voltage range and limiting said range.

Claim 22

The TTL to ECL translator of claim 18 wherein the third and fourth diode means comprise base collector shorted transistors.