Patent US4697106A successfully refreshed from Google Patents.
US4697106A
Expired / Lapsed
US
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Programmable memory circuit
Assignee: NEC Electronics Corp
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Filing: 1985-10-16
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Granted: 1987-09-29
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Expires: 2005-10-16
Abstract
Abstract A programmable memory circuit adapted to access a memory comprises a decoder responsive to address input signals, an access line, a transfer gate connected between the decoder and the access line, and a selective voltage supply circuit connected to the access line. The transfer gate is responsive to a read/write switch signal to connect the decoder to the access line in the read mode and disconnect the decoder from the access line in the write mode. The selective voltage supply circuit is also responsive to the read/write switch signal to provide on the access line different voltage levels in accordance with read/write mode. The access line assumes, in the read mode, one voltage level which is equal to the level of the output signal from the decoder and in the write mode the other voltage level.
Inventors
- 👤 Takeshi Watanabe
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 06:17
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/08; G11C16/10; G11C16/12
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
169 words
A semiconductor circuit comprising: a logic circuit having an output terminal and having at least one input terminal for receiving at least one input signal, said logic circuit selectively generating either one of first and second potentials at its output terminal in response to said at least one input signal; a signal line; connecting means for connecting said output terminal of said logic circuit to said signal line; a voltage terminal receiving a third potential higher than said first potential; switching means having a control terminal and having a current path coupled between said voltage terminal and said signal line; and control means having an input terminal connected to said signal line and an output terminal connected to said control terminal of said switching means, said control means rendering said switching means conductive when said signal line is approximately at said first potential to thereby supply said third potential to said signal line and render said switching means non-conductive when said signal line is approximately at said second potential.
Claim 2
Dependent Claim
169 words
A semiconductor circuit comprising: a logic circuit having an output terminal and having at least one input terminal for receiving at least one input signal, said logic circuit selectively generating either one of first and second potentials at its output terminal in response to said at least one input signal; a signal line; connecting means for connecting said output terminal of said logic circuit to said signal line; a voltage terminal receiving a third potential higher than said first potential; switching means having a control terminal and having a current path coupled between said voltage terminal and said signal line; and control means having an input terminal connected to said signal line and an output terminal connected to said control terminal of said switching means, said control means rendering said switching means conductive when said signal line is approximately at said first potential to thereby supply said third potential to said signal line and render said switching means non-conductive when said signal line is approximately at said second potential.
Claim 3
Dependent Claim
33 words
The circuit according to claim 1, wherein said connecting means comprises a depletion type field effect transistor having a drain-source path connected between the output of said logic circuit and said signal line.
Claim 4
Dependent Claim
86 words
The circuit according to claim 1, wherein said switching means includes a first field effect transistor of a first conductivity type having a drain-source path coupled between said voltage terminal and said signal line, and said control means includes an inverter having an input terminal coupled to said signal line and an output terminal coupled to a gate of said first transistor, said inverter including a second field effect transistor of said first conductivity type and a third field effect transistor of a second conductivity type.
Claim 5
Dependent Claim
243 words
A semiconductor circuit comprising: a logic circuit having input and output terminals and responsive to at least one input signal for generating an output signal at its output terminal, said output signal selectively having either one of a reference voltage level and a power voltage level; a signal line; an N-channel first field effect transistor having a source-drain path coupled between said signal line and said output terminal of said logic circuit; a voltage node; control means coupled to a gate of said first transistor for operatively rendering said first transistor conductive to thereby transmit said output signal of said logic circuit to said signal line; a P-channel second field effect transistor having a source-drain path coupled between said voltage node and said signal line; an N-channel third field effect transistor having a source-drain current path coupled between a reference voltage terminal receiving reference voltage and a gate of said second transistor, a P-channel fourth field effect transistor having a source-drain path coupled between said voltage node and the gate of said second transistor, gates of said third and fourth transistors being connected to said signal line; and means for supplying said voltage node with a positive voltage having the value of at least said power voltage , wherein said second transistor is rendered conductive to thereby supply said signal line with the voltage at said voltage node only when the potential on said signal line is approximately at said power voltage level.
Claim 6
Dependent Claim
243 words
A semiconductor circuit comprising: a logic circuit having input and output terminals and responsive to at least one input signal for generating an output signal at its output terminal, said output signal selectively having either one of a reference voltage level and a power voltage level; a signal line; an N-channel first field effect transistor having a source-drain path coupled between said signal line and said output terminal of said logic circuit; a voltage node; control means coupled to a gate of said first transistor for operatively rendering said first transistor conductive to thereby transmit said output signal of said logic circuit to said signal line; a P-channel second field effect transistor having a source-drain path coupled between said voltage node and said signal line; an N-channel third field effect transistor having a source-drain current path coupled between a reference voltage terminal receiving reference voltage and a gate of said second transistor, a P-channel fourth field effect transistor having a source-drain path coupled between said voltage node and the gate of said second transistor, gates of said third and fourth transistors being connected to said signal line; and means for supplying said voltage node with a positive voltage having the value of at least said power voltage , wherein said second transistor is rendered conductive to thereby supply said signal line with the voltage at said voltage node only when the potential on said signal line is approximately at said power voltage level.
Claim 7
Dependent Claim
16 words
The circuit according to claim 4, in which said first transistor is of a depletion type.
Claim 8
Dependent Claim
20 words
The circuit according to claim 4, in which said logic circuit is a decoder receiving a plurality of input signals.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-09-28 | 1991-03-30 | 1991-09-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-09-28 | 1995-03-30 | 1995-09-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-09-28 | 1999-03-30 | 1999-09-29 | $7700.00 | Window Closed / Lapsed |