Patent US4692995A successfully refreshed from Google Patents.
US4692995A
Expired / Lapsed
US
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Method of obtaining a diode whose contact tapping is self aligned with a gate
Assignee: Thales SA
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Filing: 1986-01-24
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Granted: 1987-09-15
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Expires: 2006-01-24
Abstract
Abstract A method is provided for obtaining a diode whose contact tapping is self aligned with a gate, consisting in depositing on a semiconductor substrate at least a first layer of a dielectric material, depositing on the last dielectric layer a first layer of polycrystalline silicon so as to form the gate, then a second polycrystalline silicon layer above the first layer, etching in the polycrystalline silicon layers the position of the contact diode until the dielectric layer is laid bare, oxidizing the second polycrystalline silicon layer sufficiently for the oxidized layer to completely cover the first polycrystalline silicon layer forming the gate and only to partially cover the part of the dielectric layer laid bare, and doping the portion of the substrate not covered by the oxide layer so as to form the junction of the diode.
Inventors
- 👤 Pierre Blanchard
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 09:49
CPC Classifications
H; H10; H10P; H10P76/00; H10P76/40; H10F; H10F39/00; H10F39/10; H10F39/12; H10F39/15; H10F39/153; H10P95/00; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/064; H10W20/065; Y; Y10; Y10S; Y10S148/00; Y10S148/082
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
138 words
A method of obtaining a diode whose electrical contact is self-aligned with a gate, comprising the steps of depositing on a semiconductor substrate at least a first layer of dielectric material, depositing on the last dielectric layer a localized portion of a first layer of polycrystalline silicon for forming the gate, then a second polycrystalline silicon layer above the first layer, etching in the polycrystalline silicon layers essentially at the position desired for the diode until the dielectric layer is laid bare, oxidizing the substrate sufficiently to form an oxidized layer which completely covers the localized polycrystalline silicon layer and only partially covers the bared portion of the dielectric layer and doping the portion of the substrate not covered by the oxide layer so as to form the junction of the diode in such portion of the substrate.
Claim 2
Independent Claim
138 words
A method of obtaining a diode whose electrical contact is self-aligned with a gate, comprising the steps of depositing on a semiconductor substrate at least a first layer of dielectric material, depositing on the last dielectric layer a localized portion of a first layer of polycrystalline silicon for forming the gate, then a second polycrystalline silicon layer above the first layer, etching in the polycrystalline silicon layers essentially at the position desired for the diode until the dielectric layer is laid bare, oxidizing the substrate sufficiently to form an oxidized layer which completely covers the localized polycrystalline silicon layer and only partially covers the bared portion of the dielectric layer and doping the portion of the substrate not covered by the oxide layer so as to form the junction of the diode in such portion of the substrate.
Claim 3
Dependent Claim
40 words
The method as claimed in claim 1, wherein said dielectric material layer is formed of a first silica layer and a second silicon nitride layer, the first silica layer being interposed between the second silicon nitride layer and the substrate.
Claim 4
Dependent Claim
22 words
The process as claimed in claim 2, wherein doping of the substrate takes place by ionic implantation through the dielectric material layer.
Claim 5
Dependent Claim
37 words
The method as claimed in claim 2, further including laying bare the portion of the substrate not covered by the oxide layer while removing the dielectric layer covering this portion before the doping for forming the diode.
Claim 6
Dependent Claim
28 words
The method as claimed in claim 4, wherein doping of the diode in to the substrate is achieved by using a process of diffusing impurities in the substrate.
Claim 7
Dependent Claim
25 words
The process as claimed in claim 4, wherein doping of the diode in the substrate takes place by ionic implantation of ions in the substrate.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-09-14 | 1991-03-16 | 1991-09-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-09-14 | 1995-03-16 | 1995-09-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-09-14 | 1999-03-16 | 1999-09-15 | $7700.00 | Window Closed / Lapsed |