Dielectric insulation type semiconductor integrated circuit having low withstand voltage devices and high withstand voltage devices

Claim 2

A dielectric isolation type semiconductor integrated circuit, comprising: first and second island regions, each having bottom and side surfaces, each formed of the same conductivity type semiconductor material, and said first and second island regions having substantially the same depth; each island region having a first portion of a single layer with a first predetermined impurity concentration and a second portion of a single layer with a second predetermined impurity concentration higher than said first predetermined impurity concentration; the second portion of said first island region being thinner than the second portion of said second island region, the first portion of said first island region having a greater depth than the first portion of the second island region; a first base portion and a first emitter portion formed in the first portion of each of said first and second island regions, so that a high withstand voltage transistor is formed in said first island region and a low withstand voltage transistor is formed in said second island region; first and second insulator films coating the bottom and side surfaces of said first and second island regions, respectively; and a polycrystalline semiconductor layer in contact with said first and second insulator films and integrally combining said first and second island regions.

Claim 3

A dielectric isolation type semiconductor integrated circuit as claimed in claim 1, wherein: said first base portion of said first island region constituting said high withstand voltage transistor has a depth equal to or greater than 5 μm, and said second base portion of said second island region constituting said low withstand voltage transistor has a depth equal to or less than 5 μm.

Claim 4

A dielectric isolation type semiconductor integrated circuit as claimed in claim 2, wherein said second portion of said first island region has an impurity concentration of 1×10 16 atoms/cm 3 to 1×10 18 atoms/cm 3 and said second portion of said second island region has an impurity concentration of 1×10 15 to 1×10 18 atoms/cm 3 .

Claim 5

A dielectric isolation type semiconductor integrated circuit as claimed in claim 2, wherein along the side surfaces of said first and second island regions are formed high impurity concentration portions of the same conductivity type as said island regions, said high impurity concentration portion along the side surface of said second island region having a smaller thickness than said second portion of said second island region.

Claim 6

A dielectric isolation type semiconductor integrated circuit as claimed in claim 4, wherein said second portion of said second island region includes impurities having high and low diffusion constants and said high impurity concentration portion in said first and second island regions and said second portion of said first island region includes an impurity having a low diffusion constant.

Claim 7

A semiconductor integrated circuit comprising a first region made of a single layer of monocrystalline semiconductor of one conductivity type, a second region made of a single layer of monocrystalline semiconductor of said one conductivity type and having a smaller thickness than said first region, a first high concentration region of said one conductivity type formed under and in contact with the bottom of said first region, a second high concentration region of said one conductivity type formed under and in contact with the bottom of said second region and having a larger thickness than said first high concentration region, a first base region of the other conductivity type formed in said first region, a second base region of said other conductivity type formed in said second region and having a smaller thickness than said first base region, a first and second emitter regions formed respectively in said first and second base regions, a first insulator film formed along the bottom surface and side surface of the region containing said first region and said first high concentration region, a second insulator film formed along the bottom surface and side surface of the region containing said second region and said second high concentration region, and a polycrystalline semiconductor layer formed under said first and second insulator films to combine said first and second regions and said first and second high concentration regions as an integrated circuit.

Claim 8

A semiconductor integrated circuit comprising a first region made of a single layer of monocrystalline semiconductor of one conductivity type, a second region made of a single layer of monocrystalline semiconductor of said one conductivity type and having a smaller thickness than said first region, a first high concentration region of said one conductivity type formed under and in contact with the bottom of said first region, a second high concentration region of said one conductivity type formed under and in contact with the bottom of said second region and having a larger thickness than said first high concentration region, a first base region of the other conductivity type formed in said first region, a second base region of said other conductivity type formed in said second region and having a smaller thickness than said first base region, a first and second emitter regions formed respectively in said first and second base regions, a first insulator film formed along the bottom surface and side surface of the region containing said first region and said first high concentration region, a second insulator film formed along the bottom surface and side surface of the region containing said second region and said second high concentration region, and a polycrystalline semiconductor layer formed under said first and second insulator films to combine said first and second regions and said first and second high concentration regions as an integrated circuit.

Claim 9

A semiconductor integrated circuit as claimed in claim 6, wherein said first high concentration region has a thickness of 3 to 10 μm and said second high concentration region has a thickness of 30 to 45 μm.

Claim 10

A semiconductor integrated circuit as claimed in claim 7, wherein said first region has a thickness of 25 μm to 70 μm, and said second region has a thickness of 5 μm to 30 μm.