Patent US4686559A successfully refreshed from Google Patents.
US4686559A
Expired / Lapsed
US
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Topside sealing of integrated circuit device
Assignee: Advanced Micro Devices Inc
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Filing: 1984-08-03
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Granted: 1987-08-11
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Expires: 2004-08-03
Abstract
Abstract An improved topside sealing of integrated circuit devices is disclosed which provided for hermetically sealing the top surface of the device comprising depositing a sealing layer of a nitride compound directly on the surface to be sealed. In a preferred embodiment, a protective layer may then be deposited over the nitride layer without any intervening masking steps being necessary.
Inventors
- 👤 Jacob D. Haskell
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 07:33
CPC Classifications
H; H10; H10W; H10W74/00; H10W74/10; H10W74/131; H10W74/147; H10P; H10P14/00; H10P14/60; H10P14/69; H10P14/694; H10P14/6943; H10P14/69433
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
100 words
A process for hermetically sealing the topside metallized layer of an integrated circuit device which comprises the steps of depositing and defining a topside metallized layer on the integrated circuit device, depositing from 2000 to 6000 Angstroms of a sealing layer of a nitride compound directly on the surface of said topside metallized layer to form said hermetic seal and without depositing an oxide layer between said step of depositing said topside metallized layer and said step of depositing said nitride sealing layer, and then forming a protective layer over said nitride hermetic seal to protect said nitride sealing layer.
Claim 2
Dependent Claim
100 words
A process for hermetically sealing the topside metallized layer of an integrated circuit device which comprises the steps of depositing and defining a topside metallized layer on the integrated circuit device, depositing from 2000 to 6000 Angstroms of a sealing layer of a nitride compound directly on the surface of said topside metallized layer to form said hermetic seal and without depositing an oxide layer between said step of depositing said topside metallized layer and said step of depositing said nitride sealing layer, and then forming a protective layer over said nitride hermetic seal to protect said nitride sealing layer.
Claim 3
Dependent Claim
19 words
The process of claim 1 wherein said protective layer is deposited over said nitride layer without intervening masking steps.
Claim 4
Dependent Claim
20 words
The process of claim 2 wherein said protective layer is applied over said nitride layer in the same deposition apparatus.
Claim 5
Dependent Claim
13 words
The process of claim 1 wherein said protective layer comprises an oxygen-containing material.
Claim 6
Dependent Claim
23 words
The process of claim 4 wherein said oxygen-containing compound is selected from the class consisting of silicon oxynitride, silicon oxide, and aluminum oxide.
Claim 7
Dependent Claim
13 words
The process of claim 5 wherein said oxygen-containing compound is a silicon oxide.
Claim 8
Dependent Claim
118 words
A process for hermetically sealing an integrated circuit device which comprises the steps of depositing and defining a topside metallized layer on the integrated circuit device as the final interconnect layer; depositing from 2000 to 6000 Angstroms of a sealing layer of a nitride compound to form a hermetic seal, said sealing process being characterized by the elimination of an intermediate step of depositing an oxide layer between said step of depositing said metallized layer and said step of depositing said nitride layer; and then depositing a protective layer selected from the class consisting of silicon oxynitride, silicon oxide, and aluminum oxide over said nitride hermetic seal to protect said nitride sealing layer from damage during subsequent processing.
Claim 9
Dependent Claim
118 words
A process for hermetically sealing an integrated circuit device which comprises the steps of depositing and defining a topside metallized layer on the integrated circuit device as the final interconnect layer; depositing from 2000 to 6000 Angstroms of a sealing layer of a nitride compound to form a hermetic seal, said sealing process being characterized by the elimination of an intermediate step of depositing an oxide layer between said step of depositing said metallized layer and said step of depositing said nitride layer; and then depositing a protective layer selected from the class consisting of silicon oxynitride, silicon oxide, and aluminum oxide over said nitride hermetic seal to protect said nitride sealing layer from damage during subsequent processing.
Claim 10
Dependent Claim
105 words
An integrated circuit device having an hermetic seal applied to the topside metallized layer thereof by the deposition of 2000 to 6000 Angstroms of a nitride sealing layer directly to the underlying topside metallization layer to form said hermetic seal without any intervening oxide layer between said topside metallization layer and said nitride sealing layer whereby intermediate masking and etching steps associated with deposition of said oxide layer may be eliminated and a protective layer selected from the class consisting of silicon oxynitride, silicon oxide, and aluminum oxide applied over said nitride sealing layer to protect said nitride sealing layer from damage during subsequent processing.
Claim 11
Dependent Claim
105 words
An integrated circuit device having an hermetic seal applied to the topside metallized layer thereof by the deposition of 2000 to 6000 Angstroms of a nitride sealing layer directly to the underlying topside metallization layer to form said hermetic seal without any intervening oxide layer between said topside metallization layer and said nitride sealing layer whereby intermediate masking and etching steps associated with deposition of said oxide layer may be eliminated and a protective layer selected from the class consisting of silicon oxynitride, silicon oxide, and aluminum oxide applied over said nitride sealing layer to protect said nitride sealing layer from damage during subsequent processing.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-08-10 | 1991-02-09 | 1991-08-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-08-10 | 1995-02-09 | 1995-08-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-08-10 | 1999-02-09 | 1999-08-11 | $7700.00 | Window Closed / Lapsed |