Patent US4685079A successfully refreshed from Google Patents.
US4685079A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Ripple-borrow binary subtraction circuit
Assignee: RCA Licensing Corp
•
Filing: 1984-12-14
•
Granted: 1987-08-04
•
Expires: 2004-12-14
Abstract
Abstract A binary subtracter stage for subtracting single bit binary numbers includes a first exclusive OR gate to which the numbers to be subtracted are applied. The output of the exclusive OR gate is connected to one input of a second exclusive OR gate which has a second input connected to a borrow input signal. The output of the second exclusive OR gate provides the difference between the single bit binary numbers. A borrow output signal is generated with the combination of a pass transistor coupled between the borrow input and borrow output terminals and a three state logic circuit which has its output termial connected to the borrow output terminal. The pass transistor is controlled by the output of the first exclusive OR gate and the three state logic circuit is controlled by the single bit binary numbers to be subtracted.
Inventors
- 👤 John Armer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 12:29
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/50; G06F7/501; G06F7/503
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
230 words
A binary subtracter stage for subtracting a first single bit binary number Y from a second single bit binary number X, comprising: first and second binary input terminals for applying binary numbers X and Y respectively; a borrow input and a borrow output terminal; a first XOR gate having first and second input terminals coupled to said first and second binary input terminals respectively, and having an output terminal; a second XOR gate having first and second input terminals coupled respectively to said borrow input terminal and the output terminal of said first XOR gate, and having an output terminal for producing an output signal corresponding to the difference of X minus Y; a pass transistor having a primary conduction path coupled between said borrow input and borrow output terminals, and having a control electrode coupled to the output terminal of said first XOR gate; and a three state logic circuit having first and second input terminals coupled to said first and second binary input terminals and an output terminal coupled to said borrow output terminal, said three state logic circuit generating a first logic output level according to the logic function XY, a second logic output level according to the logic function XY and a high impedance output state otherwise, where the terms X and Y connote the logic complement of the binary values of X and Y respectively.
Claim 2
Dependent Claim
230 words
A binary subtracter stage for subtracting a first single bit binary number Y from a second single bit binary number X, comprising: first and second binary input terminals for applying binary numbers X and Y respectively; a borrow input and a borrow output terminal; a first XOR gate having first and second input terminals coupled to said first and second binary input terminals respectively, and having an output terminal; a second XOR gate having first and second input terminals coupled respectively to said borrow input terminal and the output terminal of said first XOR gate, and having an output terminal for producing an output signal corresponding to the difference of X minus Y; a pass transistor having a primary conduction path coupled between said borrow input and borrow output terminals, and having a control electrode coupled to the output terminal of said first XOR gate; and a three state logic circuit having first and second input terminals coupled to said first and second binary input terminals and an output terminal coupled to said borrow output terminal, said three state logic circuit generating a first logic output level according to the logic function XY, a second logic output level according to the logic function XY and a high impedance output state otherwise, where the terms X and Y connote the logic complement of the binary values of X and Y respectively.
Claim 3
Dependent Claim
139 words
The subtracter stage set forth in claim 1 wherein the three state logic circuit comprises: first and second transistors of a first conductivity type having primary conduction paths serially coupled between said borrow output terminal and a point of potential corresponding to said first logic level, and having respective control electrodes; third and fourth transistors of a second conductivity type complementary to said first type, having primary conduction paths serially coupled between said borrow output terminal and a point of potential corresponding to said second logic level, and having respective control electrodes; means for connecting the control electrode of said first and fourth transistors to said first binary input terminal; an inverter circuit having an input terminal connected to said second binary input terminal and an output terminal connected to the control electrodes of said second and third transistors.
Claim 4
Dependent Claim
112 words
The subtraction circuit set forth in claim 1 wherein the three state logic circuit comprises: first and second transistors of first and second complementary types respectively, having principal conduction paths serially coupled between said borrow output terminal and a point of potential corresponding to said first logic level, and having respective control electrodes connected to said first and second binary input terminals respectively; third and fourth transistors of said first and second complementary types respectively, having principal conduction paths serially coupled between said borrow output terminal and a point of potential corresponding to said second logic level, and having respective control electrodes coupled to the second and first binary input terminals respectively.
Claim 5
Dependent Claim
205 words
A binary subtracter stage for subtracting a first single bit binary number Y from a second single bit binary number X comprising: first and second binary input terminals for applying binary numbers X and Y respectively; a borrow output terminal; a borrow input terminal for applying a borrow input signal Bin; exclusive OR circuitry having input terminals coupled to said first and second binary input terminals and said borrow input terminal, for producing a signal corresponding to the difference values X-Y at an output terminal thereof, responsive to the logic function (X⊕Y⊕Bin); means coupled to said first and second binary input terminals for selectively coupling the borrow output terminal to the borrow input terminal when the numbers X and Y are equal; and a three state logic circuit having first and second input terminals coupled to said first and second binary input terminals, and having an output terminal connected to said borrow output terminal, said three state logic circuit generating a logic one output state for the value of Y greater than X, generating a logic zero output state for the value of X greater than Y and generating a high impedance output state for the value of X equal to the value of Y.
Claim 6
Dependent Claim
205 words
A binary subtracter stage for subtracting a first single bit binary number Y from a second single bit binary number X comprising: first and second binary input terminals for applying binary numbers X and Y respectively; a borrow output terminal; a borrow input terminal for applying a borrow input signal Bin; exclusive OR circuitry having input terminals coupled to said first and second binary input terminals and said borrow input terminal, for producing a signal corresponding to the difference values X-Y at an output terminal thereof, responsive to the logic function (X⊕Y⊕Bin); means coupled to said first and second binary input terminals for selectively coupling the borrow output terminal to the borrow input terminal when the numbers X and Y are equal; and a three state logic circuit having first and second input terminals coupled to said first and second binary input terminals, and having an output terminal connected to said borrow output terminal, said three state logic circuit generating a logic one output state for the value of Y greater than X, generating a logic zero output state for the value of X greater than Y and generating a high impedance output state for the value of X equal to the value of Y.
Claim 7
Dependent Claim
116 words
The subtraction circuit set forth in claim 4 wherein the three state logic circuit comprises: first and second transistors of first and second complementary types respectively, having principal conduction paths serially coupled between said borrow output terminal and a point of potential corresponding substantially to said logic one output state, and having respective control electrodes connected to said first and second binary input terminals respectively; third and fourth transistors of said first and second complementary types respectively, having principal conduction paths serially coupled between said borrow output terminal and a point of potential corresponding substantially to said logic zero output state, and having respective control electrodes coupled to the second and first binary input terminals respectively.
Claim 8
Dependent Claim
142 words
The subtracter stage set forth in claim 4 wherein the three state logic circuit comprises: first and second transistors of first conductivity type having primry conduction paths serially coupled between said borrow output terminal and a point of potential corresponding to said logic one output state, and having respective control electrodes; third and fourth transistors of a second conductivity type complementary to said first conductivity type, having primary conduction paths serially coupled between said borrow output terminal and a point of potential corresponding substantially to said logic zero output state, and having respective control electrodes; means for connecting the control electrode of said first and fourth transistors to said first binary input terminal; an inverter circuit having an input terminal connected to said second binary input terminal and an output terminal connected to the control electrodes of said second and third transistors.
References Cited (Backward Citations)
US3767906A
Cited
US4052604A
Cited
US4152775A
Cited
US4357675A
Cited
US4425623A
Cited
US4439835A
Cited
US4471454A
Cited
US4523292A
Cited
US4601007A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-08-03 | 1991-02-02 | 1991-08-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-08-03 | 1995-02-02 | 1995-08-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-08-03 | 1999-02-02 | 1999-08-04 | $7700.00 | Window Closed / Lapsed |