Method of providing buried contacts for N and P channel devices in an SOI-CMOS process using a single N+polycrystalline silicon layer

Claim 1

A method of forming a silicon on insulator CMOS device using a single layer of doped polycrystalline silicon, comprising the steps of: (a) providing an insulating ase member having at least two electrically isolated islands of silicon semiconductor material one of each pair of islands being of opposite conducting type than the other of said pair, (b) forming a gate oxide in each of said islands, (c) forming an N+ polycrystalline layer over said islands and said gate oxide, (d) forming N+ regions in said islands adjacent said gate oxide, (e) exposing surfaces of said islands including a portion of each of said N+ regions and a portion of the region adjacent thereto under gate oxide, (f) masking a portion of the exposed surface in only said N-type doped island adjacent said gate oxide, (g) introducing an N+ dopant into the exposed unmasked surfaces, (h) removing said mask (i) doping siad exposed surface with a P+ type dopant sufficient to form P+ regions in the previously masked region and to retain an N+ doping level in all prior N+ doped regions, (j) forming a silicide over the surface of each said island, and (k) forming a conductive pattern coupled to the silicide of each of said gate oxide regions.

Claim 2

A method of forming a silicon on insulator CMOS device using a single layer of doped polycrystalline silicon, comprising the steps of: (a) providing an insulating ase member having at least two electrically isolated islands of silicon semiconductor material one of each pair of islands being of opposite conducting type than the other of said pair, (b) forming a gate oxide in each of said islands, (c) forming an N+ polycrystalline layer over said islands and said gate oxide, (d) forming N+ regions in said islands adjacent said gate oxide, (e) exposing surfaces of said islands including a portion of each of said N+ regions and a portion of the region adjacent thereto under gate oxide, (f) masking a portion of the exposed surface in only said N-type doped island adjacent said gate oxide, (g) introducing an N+ dopant into the exposed unmasked surfaces, (h) removing said mask (i) doping siad exposed surface with a P+ type dopant sufficient to form P+ regions in the previously masked region and to retain an N+ doping level in all prior N+ doped regions, (j) forming a silicide over the surface of each said island, and (k) forming a conductive pattern coupled to the silicide of each of said gate oxide regions.