Data processing system with an arithmetic logic unit having improved carry look ahead

Claim 1

A data processing system having an arithmetic logic unit comprising: a plurality of summation units (77), each having an addend input terminal (2), an augend input terminal (4), a carry input terminal (38), a summation output terminal (S) and a carry output terminal (50), each summation unit for receiving digital input signals on said addend input terminal, said augend input terminal and said carry input terminal and for generating digital output signals upon said summation output terminal and said carry output terminal representative of the sum of said received digital input signals, said summation output terminal communicating the digital output signal generated thereupon to the remainder of the data processing system, each summation unit further including a carry advance node (42), an exclusive OR circuit (12) connected to said addend input terminal and said augend input terminal for generating an carry propagate output signal when the digital input signals of said addend input terminal and said augent input terminal differ, and a carry switch (40) controlled by said carry propagate output signal for coupling said carry advance node to a first predetermined voltage in the absence of said carry propagate output signal; said plurality of summation units disposed sequentially in a plurality of arithmetic logic unit segments (7, 11, 15, 19), said carry output terminal of each summation unit connected to said carry input terminal of the next sequential summation unit within each of said arithmetic logic unit segment, and said carry advance node of each summation unit coupled to said carry advance node of each other summation unit within each arithmetic logic unit segment; a plurality of carry boost circuits, each having an input terminal connected to the carry output terminal of the last sequential summation unit of an arithmetic logic unit segment and having an output connected to the carry input terminal of the first sequential summation unit of the next sequential arithmetic logic unit for boosting the power of said carry output; and a plurality of carry advance circuits, each including an inverter having an input connected to said carry input terminal of said first sequential summation unit of an arithmetic logic unit segment and an output connected to said coupled carry advance nodes of said summation units of said arithmetic logic unit segment and a carry advance switch (39, 93, 61) controlled by the voltage on said coupled carry advance nodes of said summation units of said arithmetic logic unit segment for selectively connecting a second predetermined voltage representative of a carry input signal to said carry input terminal of said first sequential summation unit of the arithmetic logic unit segment next in sequence from said arithmetic logic unit segment, wherein the carry input signal applied to the carry input terminal of said first sequential summation unit of said arithmetic logic unit segment is applied to said carry input terminal of said first sequential summation unit of said next sequential arithmetic logic unit segment if all the summation units within said arithmetic logic unit segment generate a carry propagate signal.