Carry determination logic

Claim 2

A carry determination circuit for processing groups of bits, said circuit comprising the combination of first switching means for receiving a first carry input, said first switching means being activated in response to a signal from said first carry input representing a carry as being propagated from the high order bit position of said group of bits on the assumption that a carry was propagated into the low order bit position thereof, gate means for receiving a second carry input, representing a carry as being propagated from the high order bit position of said group of bits on the assumption that no carry was propagated into the low order stage thereof and for receiving a carry determination input, representing the success of a carry determination rendered on a group of bits of lower order of significance, and second switching means responsive to said first switching means and said gate for producing a signal at its output representing the condition of said gate whereby said signal being present represents a successful carry determination when said first carry input and either one of said gates inputs are present.

Claim 3

An electronic apparatus comprising a current mode logic switching circuit having a first normally conductive flowpath and a second normally nonconductive flowpath, first conditioning means operatively connected to said normally nonconductive flowpath and adapted when activated to switch the state of conduction from said first to said second flowpath; a tunnel diode switching circuit normally biased to one of its two operative states, second conditioning means operatively connected to the input of said tunnel diode switching circuit, said second conditioning means further comprising a plurality of conditioning input leads having signals selectively generated thereon which are normally incapable individually or collectively in switching said tunnel diode circuit to said second operative state; and means operatively connecting said normally conductive flowpath of said current mode logic switching circuit to the input of said tunnel diode switching circuit whereby the switching of the state of conduction from said first to said second flowpath in response to the activation of said first conditioning means is effective in further conditioning said tunnel diode switching circuit so as to cause said tunnel diode switching circuit to switch into its second operative state in response to any one of said plurality of second conditioning signals.

Claim 4

An electronic apparatus comprising a current mode logic switching circuit having a first normally conductive flowpath and a second normally nonconductive flowpath, first conditioning means operatively connected to said normally nonconductive flowpath and adapted when activated to switch the state of conduction from said first to said second flowpath; a tunnel diode switching circuit normally biased to one of its two operative states, second conditioning means operatively connected to the input of said tunnel diode switching circuit, said second conditioning means further comprising a plurality of conditioning input leads having signals selectively generated thereon which are normally incapable individually or collectively in switching said tunnel diode circuit to said second operative state; and means operatively connecting said normally conductive flowpath of said current mode logic switching circuit to the input of said tunnel diode switching circuit whereby the switching of the state of conduction from said first to said second flowpath in response to the activation of said first conditioning means is effective in further conditioning said tunnel diode switching circuit so as to cause said tunnel diode switching circuit to switch into its second operative state in response to any one of said plurality of second conditioning signals.

Claim 5

The apparatus of claim 2 wherein the biasing means for normally biasing said tunnel diode switching circuit to one of its two operative states includes an impedance member connected to the input of said tunnel diode, said biasing means further comprising a source of biasing potential precisely defined with respect to said impedance means; whereby when said tunnel diode is operative in its first operative state a positive current contribution flows through said impedance means and is joined with a negative current contribution flowing through said tunnel diode, which joint current contributions are thereafter steered into the normally conductive flowpath of said current mode logic switching circuit.

Claim 6

An electronic apparatus comprising first switching means having a first normally conductive flowpath and a second normally nonconductive flowpath, first conditioning means operatively connected to said normally nonconductive flowpath and adapted when activated to switch the state of conduction from said first to said second flowpath; second switching means including a device exhibiting negative resistance characteristics and normally biased into a particular one of its two operative states, second conditioning means operatively connected to the input of said second switching means, said second conditioning means further comprising a plurality of conditioning input leads having signals selectively generated thereon which are normally incapable individually or collectively in switching said negative resistance device to the other of its two operative states; means operatively connecting said normally conductive flowpath of said first switching means to the input of said second switching means whereby the switching of the state of conduction from said first to said second flowpath in response to the activation of said first conditioning means is effective in further conditioning said second switching means so as to cause said negative resistance device to switch to said other operative state in response to one or more of said plurality of second conditioning signals.

Claim 7

An electronic apparatus comprising first switching means having a first normally conductive flowpath and a second normally nonconductive flowpath, first conditioning means operatively connected to said normally nonconductive flowpath and adapted when activated to switch the state of conduction from said first to said second flowpath; second switching means including a device exhibiting negative resistance characteristics and normally biased into a particular one of its two operative states, second conditioning means operatively connected to the input of said second switching means, said second conditioning means further comprising a plurality of conditioning input leads having signals selectively generated thereon which are normally incapable individually or collectively in switching said negative resistance device to the other of its two operative states; means operatively connecting said normally conductive flowpath of said first switching means to the input of said second switching means whereby the switching of the state of conduction from said first to said second flowpath in response to the activation of said first conditioning means is effective in further conditioning said second switching means so as to cause said negative resistance device to switch to said other operative state in response to one or more of said plurality of second conditioning signals.

Claim 8

The apparatus of claim 4 including third switching means identical in nature to said second switching means, third conditioning means operatively connected to the input of said third switching means, said third conditioning means further comprising a plurality of conditioning input leads having signals selectively generated thereon and means operatively connecting said normally nonconductive flow path of said first switching means to the input of said third switching means whereby in the absence of a signal to said first conditioning means said last named means is effective in conditioning said third switching means so as to enable said third switching means to switch to said high voltage state in response to a signal on any one of said plurality of conditioning input leads connected thereto.

Claim 9

In an electronic apparatus, the combination of a first bistable transistor switching circuit together with at least one tunnel diode switching circuit, said bistable transistor switching circuit further comprising a pair of transistors having first electrodes connected in common, a current source connected to said common electrodes, and biasing means independently connected to second electrodes of said transistor pair, said biasing means rendering one of said pair of transistors normally conductive, means for selectively connecting input signals to the biasing electrode of said Normally nonconductive transistor, the presence of said input signal being effective in switching the current flow from said normally conductive transistor to said normally nonconductive transistor; said tunnel diode switching circuit further comprising impedance means connecting said common current biasing source at the input of said tunnel diode to said normally conductive flow path of said transistor switching circuit whereby the current flow from said common current source through said impedance means normally biases said tunnel diode to its low voltage state, a plurality of conditioning leads connected to the input of said tunnel diode, and means for selectively energizing one or more of said conditioning leads to said tunnel diode to thereby switch said tunnel diode to its second operative state only in the presence of a signal switching said normally nonconductive transistors to its conductive state.

Claim 10

In an electronic apparatus, the combination of a first bistable transistor switching circuit together with at least one tunnel diode switching circuit, said bistable transistor switching circuit further comprising a pair of transistors having first electrodes connected in common, a current source connected to said common electrodes, and biasing means independently connected to second electrodes of said transistor pair, said biasing means rendering one of said pair of transistors normally conductive, means for selectively connecting input signals to the biasing electrode of said Normally nonconductive transistor, the presence of said input signal being effective in switching the current flow from said normally conductive transistor to said normally nonconductive transistor; said tunnel diode switching circuit further comprising impedance means connecting said common current biasing source at the input of said tunnel diode to said normally conductive flow path of said transistor switching circuit whereby the current flow from said common current source through said impedance means normally biases said tunnel diode to its low voltage state, a plurality of conditioning leads connected to the input of said tunnel diode, and means for selectively energizing one or more of said conditioning leads to said tunnel diode to thereby switch said tunnel diode to its second operative state only in the presence of a signal switching said normally nonconductive transistors to its conductive state.

Claim 11

The apparatus as set forth in claim 5 further including a plurality of transistors connected in parallel with said normally nonconductive flow path of said first switching means, conditioning means connected independently to the base of each of said transistors, and means provided to selectively energize said last-mentioned conditioning means including said first conditioning means to thereby switch said second switching means to its second operative state while initiating the return of said third switching means from its high voltage state to its first operative state.

Claim 12

The apparatus of claim 6 wherein said impedance means connecting the input of said tunnel diode to the normally conductive flow path of said bistable switching circuit includes a backward diode to capacitively isolate the tunnel diode switching circuitry from the capacitive load represented by said bistable switching circuitry.

Claim 13

In a adder wherein at least two multibit operands being manipulated are segmented into a duplicated plurality of groups, the bits constituting each group being respectively connected to a plurality of stages corresponding to an optimum number of operand bits and wherein an assumed carry is forced into the low order stage of each group of one of said duplicated plurality of groups and a first signal indicative of a carry condition is established in the highest stage of one of said duplicated groups on the assumption that no carry had been propagated into the lower order stage and a second signal indicative of a carry condition is established in the highest stage of the other of said duplicated groups on the assumption that a carry had been propagated into the lower order stage, the improvement in the carry determination means associated with each of said plurality of groups for generating within one logical time unit a carry decision signal which is indicative of the true carry to be propagated therefrom, said last-named means comprising first current conditioning means, said first conditioning means including means for receiving said signal indicative of a true carry decision generated in the immediately preceding one of said plurality of groups, second current conditioning means, said second current conditioning means including means for receiving said first signal indicative of a carry generated at the output of the uppermost stage of the associated one of said plurality of groups on the assumption that no carry was propagated into the lowermost stage thereof, third current conditioning means, said third current conditioning means including means for receiving said second signal indicative of a carry generated at the output of the uppermost stage of the associated one of said plurality of groups on the assumption that a carry was propagated into the lowermost stage thereof, first logical gating means for generating at the output thereof a conditioning signal in response to one or more conditioning inputs connected thereto, said first and second current conditioning means connected as inputs to said first logical gating means, second logical gating means operative to geNerate an output in response to a predetermined number of current conditioning inputs, said output of said first logical gating means connected as one of said plurality of conditioning inputs to said second logical gating means, said third conducting means connected as a further one of said plurality of conditioning inputs to said second logical gating means whereby a signal indicative of a true carry will be generated within said one logical time unit by said second logical gating means at the output of the carry determination circuit when either said first current conditioning means is energized indicating a carry as having been propagated from the uppermost stage of the associated group on the assumption that no carry was propagated into the lowermost stage thereof, or that said second current conditioning means is energized indicating a carry as having been propagated from the uppermost stage of the associated group on the assumption that no carry was propagated into the lowermost stage thereof and third current conditioning means is energized indicating a carry as having been propagated from the highest most stage of the associated group on the assumption that a carry was propagated into the lowermost stage thereof.

Claim 14

In a adder wherein at least two multibit operands being manipulated are segmented into a duplicated plurality of groups, the bits constituting each group being respectively connected to a plurality of stages corresponding to an optimum number of operand bits and wherein an assumed carry is forced into the low order stage of each group of one of said duplicated plurality of groups and a first signal indicative of a carry condition is established in the highest stage of one of said duplicated groups on the assumption that no carry had been propagated into the lower order stage and a second signal indicative of a carry condition is established in the highest stage of the other of said duplicated groups on the assumption that a carry had been propagated into the lower order stage, the improvement in the carry determination means associated with each of said plurality of groups for generating within one logical time unit a carry decision signal which is indicative of the true carry to be propagated therefrom, said last-named means comprising first current conditioning means, said first conditioning means including means for receiving said signal indicative of a true carry decision generated in the immediately preceding one of said plurality of groups, second current conditioning means, said second current conditioning means including means for receiving said first signal indicative of a carry generated at the output of the uppermost stage of the associated one of said plurality of groups on the assumption that no carry was propagated into the lowermost stage thereof, third current conditioning means, said third current conditioning means including means for receiving said second signal indicative of a carry generated at the output of the uppermost stage of the associated one of said plurality of groups on the assumption that a carry was propagated into the lowermost stage thereof, first logical gating means for generating at the output thereof a conditioning signal in response to one or more conditioning inputs connected thereto, said first and second current conditioning means connected as inputs to said first logical gating means, second logical gating means operative to geNerate an output in response to a predetermined number of current conditioning inputs, said output of said first logical gating means connected as one of said plurality of conditioning inputs to said second logical gating means, said third conducting means connected as a further one of said plurality of conditioning inputs to said second logical gating means whereby a signal indicative of a true carry will be generated within said one logical time unit by said second logical gating means at the output of the carry determination circuit when either said first current conditioning means is energized indicating a carry as having been propagated from the uppermost stage of the associated group on the assumption that no carry was propagated into the lowermost stage thereof, or that said second current conditioning means is energized indicating a carry as having been propagated from the uppermost stage of the associated group on the assumption that no carry was propagated into the lowermost stage thereof and third current conditioning means is energized indicating a carry as having been propagated from the highest most stage of the associated group on the assumption that a carry was propagated into the lowermost stage thereof.