Forming multilayer interconnections for a semiconductor device by vapor phase growth process

Claim 1

A method of forming multilayer interconnections for a semiconductor device which comprises the steps of: (i) forming a first insulation layer on a substrate having semiconductor elements; (iia) forming a second insulation layer provided with grooves or holes therein on said first insulation layer; (ii) forming first interconnection patterns in said grooves or holes by means of a selective vapor phase growth process using a gas of a metal compound in such a manner that said first interconnection patterns cover edge parts of said second insulation layer neighboring said grooves or holes of said second insulation layer, such that the width of the edge-covering portions of said first interconnection pattern is broader than corresponding said grooves or holes, (iii) forming a third insulation layer at least on the first interconnection patterns; (iv) forming a hole in said third insulation layer to expose part of said first interconnection patterns; and (v) forming second interconnection patterns so as to be brought into contact with said first interconnection patterns through said hole, the second interconnection patterns overlapping the first interconnection patterns.

Claim 2

A method of forming multilayer interconnections for a semiconductor device which comprises the steps of: (i) forming a first insulation layer on a substrate having semiconductor elements; (iia) forming a second insulation layer provided with grooves or holes therein on said first insulation layer; (ii) forming first interconnection patterns in said grooves or holes by means of a selective vapor phase growth process using a gas of a metal compound in such a manner that said first interconnection patterns cover edge parts of said second insulation layer neighboring said grooves or holes of said second insulation layer, such that the width of the edge-covering portions of said first interconnection pattern is broader than corresponding said grooves or holes, (iii) forming a third insulation layer at least on the first interconnection patterns; (iv) forming a hole in said third insulation layer to expose part of said first interconnection patterns; and (v) forming second interconnection patterns so as to be brought into contact with said first interconnection patterns through said hole, the second interconnection patterns overlapping the first interconnection patterns.

Claim 3

A method of forming multilayer interconnections for a semiconductor device which comprises the steps of: (i) forming a first insulation layer on a substrate having semiconductor elements; (iia) forming a first interconnection pattern on said first insulation layer; (iib) forming a second insulation layer on a whole surface including said first interconnection pattern; (iic) forming a layer of another insulation material on said second insulation layer; (iid) etching said another insulation material and said second insulation layer until an upper surface of said first interconnection pattern is exposed, in flush with a neighboring etched surface of said second insulation layer; (iie) depositing a metal layer or metal silicide layer on said exposed surface of said first interconnection pattern by means of a selective vapor phase growth process using a gas of a metal compound, so that the width of said metal layer or metal silicide layer is such that it covers neighboring parts of said second insulation layer; (iii) forming a third insulation layer at least on the resultant said metal layer or metal silicide layer; (iv) forming a hole in said third insulation layer to expose part of said metal layer or metal silicide layer; and (v) forming a second interconnection pattern so as to be brought into contact with said metal layer or metal silicide layer through said hole, the second interconnection pattern overlapping the first interconnection pattern.

Claim 4

A method of forming multilayer interconnections for a semiconductor device which comprises the steps of: (i) forming a first insulation layer on a substrate having semiconductor elements; (iia) forming a first interconnection pattern on said first insulation layer; (iib) forming a second insulation layer on a whole surface including said first interconnection pattern; (iic) forming a layer of another insulation material on said second insulation layer; (iid) etching said another insulation material and said second insulation layer until an upper surface of said first interconnection pattern is exposed, in flush with a neighboring etched surface of said second insulation layer; (iie) depositing a metal layer or metal silicide layer on said exposed surface of said first interconnection pattern by means of a selective vapor phase growth process using a gas of a metal compound, so that the width of said metal layer or metal silicide layer is such that it covers neighboring parts of said second insulation layer; (iii) forming a third insulation layer at least on the resultant said metal layer or metal silicide layer; (iv) forming a hole in said third insulation layer to expose part of said metal layer or metal silicide layer; and (v) forming a second interconnection pattern so as to be brought into contact with said metal layer or metal silicide layer through said hole, the second interconnection pattern overlapping the first interconnection pattern.

Claim 7

A method of forming interconnections for a semiconductor device which comprises the steps of: (i) forming a first insulation layer on a substrate having semiconductor elements; (iia) forming a second insulation layer on said first insulation layer; (iib) selectively etching said second insulation layer, thereby forming a groove or hole in the etched region of said second insulation layer to expose an activated surface of said first insulation layer; (iic) performing a selective vapor phase growth of an electrically conductive material comprising a metal to selectively grow said conductive material on said activated surface of said first insulation layer to a thickness slightly greater than a depth of said groove or hole, so that said metal thus grown covers neighboring edge parts of said second insulation layer such that the width of said conductive material is broader than said groove or hole, thereby forming a first interconnection pattern; (iii) forming a third insulation layer at least on the first interconnection pattern; (iv) forming a hole in said third insulation layer to expose part of said first interconnection pattern; and (v) forming a second interconnection pattern so as to be brought into contact with said first interconnection pattern through said hole, the second interconnection pattern overlapping the first interconnection pattern.

Claim 8

A method of forming interconnections for a semiconductor device which comprises the steps of: (i) forming a first insulation layer on a substrate having semiconductor elements; (iia) forming a second insulation layer on said first insulation layer; (iib) selectively etching said second insulation layer, thereby forming a groove or hole in the etched region of said second insulation layer to expose an activated surface of said first insulation layer; (iic) performing a selective vapor phase growth of an electrically conductive material comprising a metal to selectively grow said conductive material on said activated surface of said first insulation layer to a thickness slightly greater than a depth of said groove or hole, so that said metal thus grown covers neighboring edge parts of said second insulation layer such that the width of said conductive material is broader than said groove or hole, thereby forming a first interconnection pattern; (iii) forming a third insulation layer at least on the first interconnection pattern; (iv) forming a hole in said third insulation layer to expose part of said first interconnection pattern; and (v) forming a second interconnection pattern so as to be brought into contact with said first interconnection pattern through said hole, the second interconnection pattern overlapping the first interconnection pattern.

Claim 9

The method according to any one of claims 1, 2 or 5 wherein said metal is one selected from the group consisting of tungsten, molybdenum, niobium, tantalum and titanium.