Patent US4670836A successfully refreshed from Google Patents.
US4670836A
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Device for detecting an overlap of operands to be accessed
Assignee: Hitachi Ltd
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Filing: 1984-06-07
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Granted: 1987-06-02
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Expires: 2004-06-07
Abstract
Abstract In order to guarantee the instruction execution sequence in a pipeline control data processing system, the present overlap detector device detects whether or not the operands overlap each other in access width units by comparing the store address specified by a store instruction with the fetch address contained in a fetch instruction following the store instruction. Moreover, the overlap detector device detects whether or not an overlap occurs in an area of the access width based on the store mark, the address in the access width unit stored in the fetch address, and the fetch data length. The overlap detector device detects the presence or absence of an overlap according to the results of operations for detecting these two overlap conditions.
Inventors
- 👤 Kanji Kubo
- 👤 Kenichi Shiozaki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 13:24
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3824; G06F9/3834
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
257 words
A device for detecting an overlap of operands to be accessed in a memory in a pipeline control data processing system, comprising: first register means for holding therein a store address of said memory specified by a store instruction; second register means for holding therein a store mask indicating the presence or absence of a store data item of an access width in byte units; third register means for holding therein a fetch address of said memory specified by a fetch instruction following said store instruction; fourth register reans for holding therein the length of a data item to be fetched by using said fetch address in said third register means as a start address for the data to be fetched; first detector means for detecting whether or not the operands to be accessed in said memory overlap each other in access width units based on said store address in said first register means and said fetch address in said third register means; second detector means for detecting whether or not said operands overlap each other in an area of said access width unit based on said store mark in said second register means, bits indicating an address in said access width unit of said fetch address in said third register means, and said fetch data length in said fourth register means; and means connected to said first and said second detector means for outputting an indication that said operands overlap each other when said first detector means and said second detector means detect an overlap, respectively.
Claim 2
Independent Claim
257 words
A device for detecting an overlap of operands to be accessed in a memory in a pipeline control data processing system, comprising: first register means for holding therein a store address of said memory specified by a store instruction; second register means for holding therein a store mask indicating the presence or absence of a store data item of an access width in byte units; third register means for holding therein a fetch address of said memory specified by a fetch instruction following said store instruction; fourth register reans for holding therein the length of a data item to be fetched by using said fetch address in said third register means as a start address for the data to be fetched; first detector means for detecting whether or not the operands to be accessed in said memory overlap each other in access width units based on said store address in said first register means and said fetch address in said third register means; second detector means for detecting whether or not said operands overlap each other in an area of said access width unit based on said store mark in said second register means, bits indicating an address in said access width unit of said fetch address in said third register means, and said fetch data length in said fourth register means; and means connected to said first and said second detector means for outputting an indication that said operands overlap each other when said first detector means and said second detector means detect an overlap, respectively.
Claim 3
Dependent Claim
102 words
A device for detecting an overlap of operands to be accessed in a memory in a pipeline control data processing system according to claim 1, wherein said second detector means comprises: first indiction means for indicating the presence or absence of said store data in each division unit obtained by subdividing by n said access width based on said store mark; second indication means for indicating said division unit to be fetched by said fetch address and said fetch data length; and means for detecting an overlap in said access unit based on information stored in said first and second indication means.
Claim 4
Dependent Claim
49 words
A device for detecting an overlap of operands to be accessed in a memory in a pipeline control data processing system according to claim 2, wherein each said first indication means comprises means for ORing said store marks in each of said division units with every other division unit.
Claim 5
Dependent Claim
34 words
A device for detecting an overlap of operands to be accessed in a memory in a pipeline control data processing system according to claim 1, wherein said store and fetch addresses indicate logical addresses.
Claim 6
Dependent Claim
101 words
A device for detecting an overlap of operands to be accessed in a memory in a pipeline control data processing system according to claim 4, wherein said store address and fetch address each comprise a page address portion, and a portion for an address in the access width unit; and said first detection means coxprises means for detecting a matching between said store address in said first register means and said fetch address in said third register means and a matching between said address in a page of said store address and said address in a page of said fetch address.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-06-01 | 1990-12-01 | 1991-06-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-06-01 | 1994-12-01 | 1995-06-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-06-01 | 1998-12-01 | 1999-06-02 | $7700.00 | Window Closed / Lapsed |