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US4660171A
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Apparatus and method using a programmable logic array for decoding an operation code and providing a plurality of sequential output states
Assignee: International Business Machines Corp
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Filing: 1981-12-21
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Granted: 1987-04-21
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Expires: 2001-12-21
Abstract
Abstract Apparatus and method for decoding computer operation codes. The operation code is decoded into a single product term in the AND array of a programmable logic array. That single product term is then processed through a clock driven sequencer to generate a plurality of sequential product terms. These sequential product terms are decoded by the OR array of the programmable logic array to generate a plurality of sequential time states comprising the decoded operation code.
Inventors
- 👤 Victor S. Moore
- 👤 Wayne R. Kraft
- 👤 Joseph C. Rhodes, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 19:34
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/22; G06F9/223
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
167 words
Apparatus for decoding a selectable computer operation code, said apparatus including clock means for generating sequential timing signals, and a programmable logic array comprising an AND array to which a selected operation code is provided as an input and an OR array from which decoded output signals appear as sequential output signals, characterized by: the AND array providing for each selectable operation code a corresponding unique output; a plurality of sequencer means, one sequencer means for each unique output from the AND array, at least one sequencer means being coupled to said clock means and being responsive to said sequential timing signals produced by said clock means and to its corresponding unique output from said AND array for generating for the corresponding operation code a plurality of sequential time state signals comprising the input to said OR array; and said OR array being responsive to said sequential time state signals for generating a plurality of decoded sequential output signals representing a decoding of said corresponding operation code.
Claim 2
Dependent Claim
167 words
Apparatus for decoding a selectable computer operation code, said apparatus including clock means for generating sequential timing signals, and a programmable logic array comprising an AND array to which a selected operation code is provided as an input and an OR array from which decoded output signals appear as sequential output signals, characterized by: the AND array providing for each selectable operation code a corresponding unique output; a plurality of sequencer means, one sequencer means for each unique output from the AND array, at least one sequencer means being coupled to said clock means and being responsive to said sequential timing signals produced by said clock means and to its corresponding unique output from said AND array for generating for the corresponding operation code a plurality of sequential time state signals comprising the input to said OR array; and said OR array being responsive to said sequential time state signals for generating a plurality of decoded sequential output signals representing a decoding of said corresponding operation code.
Claim 3
Dependent Claim
123 words
Apparatus for decoding a selectable computer operation code, comprising: counter means for generating a plurality of sequential clock signals; AND array means for generating for each selectable operation code a single unique product term; a plurality of sequencer means, each sequencer means being responsive to said counter means for generating from a corresponding unique product term a plurality of sequenced product terms for a selected operation code; and OR array means responsive to said sequenced product terms for generating sequenced output signals representing a decoding of an operation code input to said AND array; whereby a plurality of sequenced output signals may be generated out of said OR array means for one pass of a selected operation code through said AND array means.
Claim 4
Dependent Claim
123 words
Apparatus for decoding a selectable computer operation code, comprising: counter means for generating a plurality of sequential clock signals; AND array means for generating for each selectable operation code a single unique product term; a plurality of sequencer means, each sequencer means being responsive to said counter means for generating from a corresponding unique product term a plurality of sequenced product terms for a selected operation code; and OR array means responsive to said sequenced product terms for generating sequenced output signals representing a decoding of an operation code input to said AND array; whereby a plurality of sequenced output signals may be generated out of said OR array means for one pass of a selected operation code through said AND array means.
Claim 5
Dependent Claim
38 words
The apparatus of claim 2 wherein said sequencer means includes a plurality of binary decoder means, with a decoder means provided for each unique product term, for generating unique sequenced product terms corresponding to each unique product term.
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USPTO Annuity & Maintenance Windows
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| 3.5 Years (Year 4) | 1990-04-20 | 1990-10-20 | 1991-04-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-04-20 | 1994-10-20 | 1995-04-21 | $3760.00 | Window Closed / Lapsed |
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