Programmable logic array

Claim 1

A single plane programmable logic array (PLA) having a reference potential rail, a first series of logic input terminals, a second series of logic input terminals, and a regular row-column array of switching FET structures, the PLA being programmable to render the switching FET structures operable as switching FETs at selected positions of the row-column matrix, the resulting switching FETs being source-to-drain series connected in individual array columns and having their gates common connected in rows, each column having a respective PMOS control FET at a first end with a source terminal thereof connected to said reference potential rail, respective input logic terminals of said first series being commonly connected to the gates of a respective row of switching FETs, each column having a respective NMOS control FET at a second end, the NMOS control FETs having source terminals connected to respective input logic terminals of said second series, the programmed PLA having an output end having column outputs, each dependent on logic states at the first and second series of logic input terminals and on the presence of switching FETs at the selected positions in the column, and wherein at the first end of each column, a drain-drain connection exists between the PMOS control FET and the adjacent switching FET, said programming being such as to produce at the column outputs of the array at least one conducting lead joining at least two of said drain-drain connections whereby the logical OR of the column outputs of joined columns is available.