US3945000A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Series logic circuit arrangement using a plurality of complementary IGFET's
Assignee: Toshiba Corp
•
Filing: 1974-07-30
•
Granted: 1976-03-16
•
Expires: 1994-07-30
Abstract
Abstract A series logic circuit arrangement using a plurality of complementary IGFET's and comprising a plurality of series connected logic circuits, each of the logic circuits being designed to effect a predetermined logic function with respect to input binary coded signals by using at least one P channel IGFET and one N channel IFGET. In the negative logic system, the P channel IGFET's are arranged on a semiconductor substrate according to a logic equation of minterm-type expression, and the N channel IGFET's are arranged on the substrate according to a logic equation of maxterm-type expression, and, in the positive logic system, the N channel IGFET's are provided on the substrate according to the logic equation of minterm-type expression, and the P channel IGFET's are disposed on the substrate according to the logic equation of maxterm-type expression, thereby admitting of integrating the P and N channel IGFET's on the substrate within a smallest possible area.
Inventors
- 👤 Yasoji Suzuki
- 👤 Kenshi Manabe
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 15:27
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/1778; H03K19/08; H03K19/094; H03K19/0944; H03K19/0948; H10; H10B; H10B20/00
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
169 words
In a series logic circuit arrangement using a plurality of P and N channel IGFET's and comprising a plurality of series logic circuits to which a plurality of input binary coded signals are applied, each of said logic circuits being designed to effect a predetermined logic function with respect to any ones of the plurality of input binary coded signals by using at least one P channel IGFET and one N channel IGFET, the improvement in that said P channel IGFET's and N channel IGFET's are arranged according to positive and negative logic systems with respect to the plurality of input binary coded signals, in the negative logic system, said P channel IGFET's being arranged according to a logic equation of minterm-type expression and said N channel IGFET's according to a logic equation of maxterm-type expression, and, in the positive logic system, said P channel IGFET's being provided according to a logic equation of maxterm-type expression and said N channel IGFET's according to a logic equation of minterm-type expression.
Claim 2
Dependent Claim
169 words
In a series logic circuit arrangement using a plurality of P and N channel IGFET's and comprising a plurality of series logic circuits to which a plurality of input binary coded signals are applied, each of said logic circuits being designed to effect a predetermined logic function with respect to any ones of the plurality of input binary coded signals by using at least one P channel IGFET and one N channel IGFET, the improvement in that said P channel IGFET's and N channel IGFET's are arranged according to positive and negative logic systems with respect to the plurality of input binary coded signals, in the negative logic system, said P channel IGFET's being arranged according to a logic equation of minterm-type expression and said N channel IGFET's according to a logic equation of maxterm-type expression, and, in the positive logic system, said P channel IGFET's being provided according to a logic equation of maxterm-type expression and said N channel IGFET's according to a logic equation of minterm-type expression.
Claim 3
Dependent Claim
47 words
In a series logic circuit arrangement claimed in claim 1, the further improvement in that said P channel IGFET's and N channel IGFET's are all integrated on a semiconductor substrate right below the corresponding passageways of the plurality of input binary coded signals disposed on said substrate.
Claim 4
Dependent Claim
35 words
In a series logic circuit arrangement claimed in claim 1, which constitutes a decoder apparatus designed to give forth a decoded logic output bearing a predetermined relationship with a plurality of input binary coded signals.
Claim 5
Dependent Claim
74 words
In a series logic circuit arrangement claimed in claim 3, the further improvement in that said decoder apparatus comprises a binary coded decimals to 7-segment decoder apparatus designed to select any segment of a digit display device which is constituted by 7-segments formed in a substantially 8-shape capable of indicating any of the digits of 0 through 9 in accordance with a predetermined logic combination of a plurality of input binary coded decimal signals.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-03-16 | 1979-09-15 | 1980-03-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-03-16 | 1983-09-15 | 1984-03-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-03-16 | 1987-09-15 | 1988-03-16 | $7700.00 | Window Closed / Lapsed |