Mos memory decode

Claim 2

A digital decoding system for selectively decoding a multibit digital input signal, said system including first and second reference signal input means and at least one system output means, comprising in combination: a. a first plurality of solid state switching circuits, each having at least one insulated gate transistor of a first channel type; b. a second plurality of solid state switching circuits, each having at least one insulated gate transistor of said first channel type; wherein c. each of said first and second switching circuits have at least one signal input terminal and first and second switch terminals, and wherein d. said first switching circuits are cascade coupled between said first reference signal means and said system output means such that at least one of said first switch terminals is coupled to said first reference signal, at least one of said second switch terminals is coupled to said system output means, and the remaining of said second switch terminals are connected to at least one of said first switch terminals; and wherein e. said second plurality of switching circuits are connected such that at least one of said second switch terminals is connected to said second reference signal input means and in common with the remaining of said second switch terminals, and at least one of said first switch terminals is connected to said system output means with others of said first switch terminals being connected to at least one of said first switch terminals of said first switching circuit by means other than one of said first insulated gate transistors; and wherein f. when a preselected value of said input signal is coupled to said system, said first switching circuits are OPEN and said second switching circuits are CLOSED, thereby coupling said first reference signal to said system output means; and wherein g. for substantially all other values of said input signal coupled to said system, at least one of said first switching circuits is CLOSED and at least one of said second switching circuits is OPEN, thereby coupling said second reference signal to said system''s output means.

Claim 3

A digital decoding system for selectively decoding a multi-bit digital input signal, said system including first and second reference signal input means and at least one system output means, comprising in combination: a. a first plurality of solid state switching circuits, each having at least one insulated gate transistor of a first channel type; b. a second plurality of solid state switching circuits, each having at least one insulated gate transistor of said first channel type; wherein c. each of said first and second switching circuits have at least one signal input terminal and first and second switch terminals, and wherein d. said first switching circuits are cascade coupled between said first reference signal means and said system output means such that at least one of said first switch terminals is coupled to said first reference signal, at least one of said second switch terminals is coupled to said system output means, and the remaining of said second switch terminals are connected to at least one of said first switch terminals; and wherein e. said second plurality of switching circuits are connected such that at least one of said second switch terminals is connected to said second reference signal input means and in common with the remaining of said second switch terminals, and at least one of said first switch terminals is connected to said system output means with others of said first switch terminals being connected to at least one of said first switch terminals of said first switching circuit by means other than one of said first insulated gate transistors; and wherein f. when a preselected value of said input signal is coupled to said system, said first switching circuits are OPEN and said second switching circuits are CLOSED, thereby coupling said first reference signal to said system output means; and wherein g. for substantially all other values of said input signal coupled to said system, at least one of said first switching circuits is CLOSED and at least one of said second switching circuits is OPEN, thereby coupling said second reference signal to said system''s output means.

Claim 4

A digital decoding system for selectively decoding a multi-bit digital input signal, said system including first and second reference signal input means and at least one system output means, comprising in combination: a. a first plurality of solid state switching circuits, each having at least one insulated gate transistor of a first channel type; b. a second plurality of solid state switching circuits, each having at least one insulated gate transistor of said first channel type; wherein c. each of said first and second switching circuits have at least one signal input terminal and first and second switch terminals, and wherein d. said first switching circuits are cascade coupled between said first reference signal means and said system output means such that at least one of said first switch terminals is coupled to said first reference signal, at least one of said second switch terminals is coupled to said system output means, and the remaining of said second switch terminals are connected to at least one of said first switch terminals; and wherein e. said second plurality of switching circuits are connected such that at least one of said second switch terminals is connected to said second reference signal input means and in common with the remaining of said second switch terminals, and at least one of said first switch terminals is connected to said system output means with others of said first switch terminals being connected to at least one of said first switch terminals of said first switching circuit by means other than one of said first insulated gate transistors; and wherein f. when a preselected value of said input signal is coupled to said system, said first switching circuits are OPEN and said second switching circuits are CLOSED, thereby coupling said first reference signal to said system output means; and wherein g. for substantially all other values of said input signal coupled to said system, at least one of said first switching circuits is CLOSED and at least one of said second switching circuits is OPEN, thereby coupling said second reference signal to said system''s output means.

Claim 5

A digital decoding system in accordance with claim 1 wherein said first channel type is P-channel.

Claim 6

A digital decoding system in accordance with claim 1 wherein said first channel type is N-channel.

Claim 7

A digital decoding system in accordancE with claim 1 wherein said first and second switching circuits are formed within a common semiconductor substrate, and selectively interconnected by selectively doped regions within said common semiconductor substrate.

Claim 8

A digital decoding system for selectively decoding a multi-bit digital input signal, said system including first and second reference signal input means and at least one system output means, comprising in combination: a. a first plurality of insulated gate field effect transistors of a first channel type, each having source, drain and gate terminals; and b. a second plurality of insulated gate field effect transistors of said first channel type, each having source, drain and gate terminals; wherein c. said first plurality of insulated gate field effect transistors are source-to-drain cascade connected with the drain terminal of the first insulated gate field effect transistor in the cascade being connected to said first reference signal means and the source terminal of the last insulated gate field effect transistor in the cascade being connected to said system output means; and wherein d. said second plurality of insulated gate field effect transistors are connected such that the source terminal of each of said second plurality of transistors is connected in common to said second reference signal means with at least one of the drain terminals of said second plurality of transistors being connected to said systems output means with other drain terminals connected by means other than one of said first insulated gate field effect transistors to a respective source terminal of a transistor of said first plurality of transistors; and wherein e. when a predetermined value of said digital input signal is coupled to the gate of said first and second pluralities of transistors, said reference signal is coupled to said system output means; responsive to a second predetermined value of said input signal said second reference signal is coupled to said output means through one of said second plurality of transistors and the source-drain path of at least one of said first plurality of transistors, and responsive to a third predetermined value of said input said second reference signal is coupled to said output means only through one of said second plurality of transistors.

Claim 9

A digital decoding system for selectively decoding a multi-bit digital input signal, said system including first and second reference signal input means and at least one system output means, comprising in combination: a. a first plurality of insulated gate field effect transistors of a first channel type, each having source, drain and gate terminals; and b. a second plurality of insulated gate field effect transistors of said first channel type, each having source, drain and gate terminals; wherein c. said first plurality of insulated gate field effect transistors are source-to-drain cascade connected with the drain terminal of the first insulated gate field effect transistor in the cascade being connected to said first reference signal means and the source terminal of the last insulated gate field effect transistor in the cascade being connected to said system output means; and wherein d. said second plurality of insulated gate field effect transistors are connected such that the source terminal of each of said second plurality of transistors is connected in common to said second reference signal means with at least one of the drain terminals of said second plurality of transistors being connected to said systems output means with other drain terminals connected by means other than one of said first insulated gate field effect transistors to a respective source terminal of a transistor of said first plurality of transistors; and wherein e. when a predetermined value of said digital input signal is coupled to the gate of said first and second pluralities of transistors, said reference signal is coupled to said system output means; responsive to a second predetermined value of said input signal said second reference signal is coupled to said output means through one of said second plurality of transistors and the source-drain path of at least one of said first plurality of transistors, and responsive to a third predetermined value of said input said second reference signal is coupled to said output means only through one of said second plurality of transistors.

Claim 10

A digital decoding system in accordance with claim 5 wherein said first channel type is P-channel.

Claim 11

A digital decoding system in accordance with claim 5 wherein said first channel type is N-channel.