CMOS low-power TTL-compatible input buffer

Claim 2

A CMOS buffer amplifier circuit having first and second supply rails connectable to a source of operating power, an input terminal connectable to a source of logic signals and an output terminal for producing an inverted version of said logic signals, said circuit comprising: a first IGFET having a source coupled to said second supply rail, a gate coupled to said input terminal and a drain coupled to said output terminal; a second IGFET of the same conductivity type at the first IGFET, having a source coupled to said input terminal, a gate coupled to a source of reference potential and a drain; and third and fourth complementary IGFET's having their sources coupled to said first supply rail, their drains coupled respectively to said first and second IGFET's and their gates cross coupled to the opposite drains to create a latching load configuration.

Claim 3

The circuit of claim 1 further including means for coupling the back gate of said second IGFET to said second supply rail whereby the body effect increases the effective gain of said second IGFET.

Claim 4

The circuit of claim 1 wherein said first and second IGFET's are N channel transistors and said pair of complementary IGFET's are P channel transistors.

Claim 5

The circuit of claim 1 wherein said source of reference potential is operated at close to one IGFET threshold above about 1-2 volts whereby said circuit responds to TTL logic input signals.

Claim 6

The circuit of claim 1 wherein said source of reference potential appears at a reference potential terminal and is developed in a circuit comprising: a first BJT having its collector coupled to said reference potential terminal and its emitter coupled to said second supply rail; a second BJT having its collector coupled to said first supply rail and its emitter coupled to said reference potential terminal; a third BJT having its emitter coupled to said second supply rail and its collector and base coupled together to the base of said first BJT to form a current mirror therewith; a fourth BJT having its collector and base coupled together and to the base of said second bipolar transistor to form a current mirror therewith; a fifth IGFET of the same conductivity type as said first IGFET having its drain coupled to the emitter of said fourth BJT, its source coupled by way of a first resistor to said collector of said third BJT and its gate coupled to said reference potential terminal; and means for passing a controlled current through said third and fourth BJT's and said fifth IGFET.

Claim 7

The circuit of claim 5 wherein said means for passing a controlled current comprises: a sixth IGFET of said complementary type having its source coupled to said first supply rail and its drain coupled to said fourth BJT collector and base terminals; a seventh IGFET of said complementary type having its source coupled to said first supply rail and its gate and drain coupled together to said sixth IGFET gate to form a current mirror therewith; and a second resistor coupled between said seventh IGFET drain and said second supply rail to establish an input current for said reference circuit.

Claim 8

The circuit of claim 1 wherein said source of reference potential appears at a reference potential terminal and is developed in a circuit comprising: a fifth IGFET of said same conductivity type and having its drain coupled to said reference potential terminal, its source coupled to said second supply rail and a gate; a sixth IGFET of said same conductivity type and having its source coupled to said reference terminal, its drain coupled to said first supply rail and a gate; a seventh IGFET of said same conductivity type and having its source coupled to said second supply rail and its gate and drain coupled to said fifth IGFET to provide a current mirror therewith; an eighth IGFET of said same conductivity type and having its gate and drain coupled to said gate of said sixth IGFET to provide a current mirror therewith; a ninth IGFET having its drain coupled to the source of said eighth IGFET, its gate coupled to said reference potential terminal and its source coupled via a first resistor to the drain of said seventh IGFET; and means for passing a controlled current through said seventh, eighth and ninth IGFET's.

Claim 9

The circuit of claim 7 wherein said means for passing a controlled current comprises: a tenth IGFET of said complementary type and having its source coupled to said first supply rail, its drain coupled to said drain of said eighth IGFET and a gate; an eleventh IGFET of said complementary type and having its source coupled to said first supply rail, its gate and drain coupled together to said gate of said tenth IGFET to provide a current mirror therewith; and a second resistor coupled between said drain of said eleventh IGFET and said second supply rail.