Patent US4654864A successfully refreshed from Google Patents.
US4654864A
Expired / Lapsed
US
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Phase synchronizing circuit
Assignee: NEC Corp
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Filing: 1983-04-19
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Granted: 1987-03-31
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Expires: 2003-04-19
Abstract
Abstract A fast pull-in phase synchronizing circuit, including a phaselock loop, having an extended pull-in range. The phase synchronizing circuit includes, besides a conventional phaselock loop, at least a π/2+nπ (n being an integer) phase shifter, a mixer, a low pass filter and another mixer. The phase shifter receives the output of the phaselock loop VCO, the output of the phase shifter being multiplied in the mixer with the circuit input signal. This multiplied signal is applied as an input to the low pass filter, which produces a low frequency output proportional to the frequency difference between the input and output signals. This low frequency signal is mixed in the other mixer with the circuit input signal to produce the phaselock loop input signal. The phaselock loop input is phase compared with the VCO output in the phaseback loop phase comparator. This phase comparator output has by reason of the phase synchronizing circuit of the invention two components, one representing the frequency discrimination characteristic of the circuit, the other the phase comparison characteristic. When in its unsynchronized state, the circuit of the invention operates as an automatic frequency control circuit causing the VCO oscillating frequency to vary in a direction to decrease the frequency error, W in -W ont . Once the frequency error has been reduced to the pull-in range, i.e. the synchronized range, the circuit of the invention operates to produce phase synchronization.
Inventors
- 👤 Osamu Ichiyoshi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 18:06
CPC Classifications
H; H04; H04L; H04L27/00; H04L27/18; H04L27/22; H04L27/227; H04L27/2271; H04L27/2272; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/10; H03L7/113
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
142 words
A phase synchronizing circuit having a voltage controlled oscillator for generating an output signal in response to a control voltage, a phase comparator for phase-comparing said output signal with a first signal to provide a second signal and a loop filter for smoothing said second signal to provide said control voltage, comprising: a phase shifter for phase-shifting said output signal by (π/2)+nπ (n being an integer) to produce a third signal; a first mixer for mixing said third signal with an input signal to provide a fourth signal; a low-pass filter for selecting a low frequency component out of said fourth signal and providing a fifth signal whose phase is delayed an amount proportioned to the frequency difference between said input and output signals; and a second mixer for mixing said fifth signal with said input signal to provide said first signal.
Claim 2
Dependent Claim
142 words
A phase synchronizing circuit having a voltage controlled oscillator for generating an output signal in response to a control voltage, a phase comparator for phase-comparing said output signal with a first signal to provide a second signal and a loop filter for smoothing said second signal to provide said control voltage, comprising: a phase shifter for phase-shifting said output signal by (π/2)+nπ (n being an integer) to produce a third signal; a first mixer for mixing said third signal with an input signal to provide a fourth signal; a low-pass filter for selecting a low frequency component out of said fourth signal and providing a fifth signal whose phase is delayed an amount proportioned to the frequency difference between said input and output signals; and a second mixer for mixing said fifth signal with said input signal to provide said first signal.
Claim 3
Dependent Claim
71 words
A phase synchronizing circuit as claimed in claim 1, further comprising first means connected to the output of said first mixer for detecting the synchronization and asynchronization of said phase synchronizing circuit to provide sixth and seventh signals; and second means responsive to said sixth signal for increasing the time constant of said low pass filter and to said seventh signal for decreasing said time constant of said low pass filter.
Claim 4
Dependent Claim
110 words
A phase synchronizing circuit as claimed in claim 1, further comprising first means connected to the output of said first mixer for detecting the synchronization and asynchronization of said phase synchronizing circuit to provide said sixth and seventh signals, second means for generating a constant voltage, and third means responsive to the output of said low-pass filter and said sixth and seventh signals for supplying said constant voltage to said second mixer and blocking the output of said low-pass filter in response to said sixth signal, and for supplying the output of said low-pass filter to said second mixer and blocking said constant voltage in response to said seventh signal.
Claim 5
Dependent Claim
104 words
A phase synchronizing circuit as claimed in claim 2 wherein said low pass filter has a variable time constant and wherein: said first means comprises another low pass filter means, receiving the output of said first mixer, for producing a signal having a phase proportional to the frequency difference between the input signal and said output signal; said another low pass filter means producing said sixth signal when the said frequency difference is sufficiently small to signify synchronization and producing said seventh signal when said frequency difference is too large to allow pull-in thereby signifying asynchronization; and and second means comprises a level detector.
Claim 6
Dependent Claim
179 words
A phase synchronizing circuit as claimed in claim 3 wherein: said first means comprises another low pass filter means, receiving the output of said first mixer, for producing a signal having a phase proportional to the frequency difference between the input signal and said output signal; said another low pass filter means producing said sixth signal when said frequency difference is sufficiently small to signify synchronization and producing said seventh signal when said frequency difference is too large to allow pull-in thereby signifying asynchronization; and said means for supplying comprises a level detector connected to the output of said another low pass filter and a switch means, connected to the output of said level detector, said switch means assuming a first or second state responsive to the output of said level detector, in said first state said switch means supplying said constant voltage to said second mixer while blocking the output of said low pass filter, in said second state said switch means supplying the output of said low-pass filter to said second mixer while blocking said constant voltage.
Claim 7
Dependent Claim
182 words
A phase synchronizing circuit adapted to receive an input signal and having a phaselock loop which includes a voltage controlled oscillator generating an output signal in response to a control voltage, a phase comparator means for comparing said output signal with a first signal to provide a second signal and a loop filter means receiving said second signal and producing at its output said control signal, said phase synchronizing circuit further including: phase shifter means for phase shifting said output signal by π/2+nπ (n being an integer); first mixer means for mixing the input signal with the output of said phase shifter means; low pass filter means connected to the output of said first mixer means for producing a signal having a phase proportional to the frequency difference between the input signal and said output signal; and second mixer means for mixing the output of said low pass filter means and the input signal to produce said first signal; said second signal having one component representative of the circuit frequency discrimination characteristic and another component representative of the circuit phase comparison characteristic.
Claim 8
Dependent Claim
182 words
A phase synchronizing circuit adapted to receive an input signal and having a phaselock loop which includes a voltage controlled oscillator generating an output signal in response to a control voltage, a phase comparator means for comparing said output signal with a first signal to provide a second signal and a loop filter means receiving said second signal and producing at its output said control signal, said phase synchronizing circuit further including: phase shifter means for phase shifting said output signal by π/2+nπ (n being an integer); first mixer means for mixing the input signal with the output of said phase shifter means; low pass filter means connected to the output of said first mixer means for producing a signal having a phase proportional to the frequency difference between the input signal and said output signal; and second mixer means for mixing the output of said low pass filter means and the input signal to produce said first signal; said second signal having one component representative of the circuit frequency discrimination characteristic and another component representative of the circuit phase comparison characteristic.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-03-30 | 1990-09-29 | 1991-03-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-03-30 | 1994-09-29 | 1995-03-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-03-30 | 1998-09-29 | 1999-03-31 | $7700.00 | Window Closed / Lapsed |