Patent US1818099A successfully refreshed from Google Patents.
Patent US4653074A successfully refreshed from Google Patents.
US4653074A
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Bit sync generator
Assignee: Unisys Corp
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Filing: 1985-01-24
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Granted: 1987-03-24
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Expires: 2005-01-24
Abstract
Abstract A system for synchronizing information bits to any frequency signal chain with low jitter correction and adapted for gate array implementation.
Inventors
- 👤 Dan M. Griffin
- 👤 Clifford T. Johnson
- 👤 Larry J. Miller
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 13:22
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/02; H04L7/033; H04L7/0331
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
195 words
A synchronizer circuit comprising, input means (VIDEO) for supplying input signals, clock means (14) for supplying clock signals, pre-scaler means (10) for receiving and altering the frequency of said clock signals from said clock means to produce scaled clock signals and return said scaled clock signals to said clock means, control means (12) connected to said pre-scaler means to control the operation thereof, divider circuit means (15) connected to receive said clock signals from said clock means and to divide said clock signals by selected division factors, counter means (18) connected to receive the divided clock signals from said divider circuit means and to provide signals to said divider circuit means to selectively alter said division factors until synchronism is achieved between said input signals and said clock signals, detector means (17) connected to said input means for detecting the presence of input signals and producing output signals which are supplied to said counter means and thereby control the operation of said divider circuit means, and sync lock circuit means (20) connected to said clock means and said detector means and operative to indicate a synchronized condition between said input signals and said clock signals.
Claim 2
Dependent Claim
195 words
A synchronizer circuit comprising, input means (VIDEO) for supplying input signals, clock means (14) for supplying clock signals, pre-scaler means (10) for receiving and altering the frequency of said clock signals from said clock means to produce scaled clock signals and return said scaled clock signals to said clock means, control means (12) connected to said pre-scaler means to control the operation thereof, divider circuit means (15) connected to receive said clock signals from said clock means and to divide said clock signals by selected division factors, counter means (18) connected to receive the divided clock signals from said divider circuit means and to provide signals to said divider circuit means to selectively alter said division factors until synchronism is achieved between said input signals and said clock signals, detector means (17) connected to said input means for detecting the presence of input signals and producing output signals which are supplied to said counter means and thereby control the operation of said divider circuit means, and sync lock circuit means (20) connected to said clock means and said detector means and operative to indicate a synchronized condition between said input signals and said clock signals.
Claim 3
Dependent Claim
37 words
The synchronizer circuit recited in claim 1 wherein, said clock means includes clock multiplexer (mux) means connected (14) to said control means to receive control signals therefrom and to selectively supply clock signals to said pre-scaler means.
Claim 4
Dependent Claim
99 words
The synchronizer circuit recited in claim 2 wherein, said clock mux includes latch means connected to said control means and operative to select the mode of operation of said clock mux, multiplexer means connected to receive and transmit one of a plurality of clock signals in response to the signals stored in said latch means, and logic circuits connected to receive control signals from said pre-scaler means, said latch mean, said multiplexer, and said divider circuit means which control signals are representative of the conditions of these respective means and operative to produce a plurality of system clock signals.
Claim 5
Dependent Claim
38 words
The synchronizer circuit recited in claim 1 wherein, said detector means includes transition detector means for detecting the presence of an input signal and producing signals which indicate whether said input signal leads or lags said clock signals.
Claim 6
Dependent Claim
42 words
The synchronizer circuit recited in claim 4 wherein, said detector means includes data active circuit means connected to said transition detector means for detecting the presence of a transition at said input means and producing an output signal which indicates data activity.
Claim 7
Dependent Claim
78 words
The synchronizer circuit recited in claim 5 wherein, said data active circuit includes logic circuitry connected to said transition detector to indicate a transition at said input means, and ripple counter means which operates to count a preselected number of counts and produce an output signal which indicates no signal activity unless said logic circuitry produces a pulse which indicates a transtion at said input means prior to said ripple counter means reaching said preselected number of counts.
Claim 8
Dependent Claim
34 words
The synchronizer circuit recited in claim 4 wherein, said transition detector means includes a plurality of serially connected flip-flop circuits connected to pass said input signals therethrough whereby a settled signal condition is assured.
Claim 9
Dependent Claim
72 words
The synchronizer circuit recited in claim 1 wherein, said pre-scaler means comprises input latch circuit means connected to said control means to store information from said control means, further counter means connected to said latch circuit means thereby to have a count value stored therein for counting clock signals from said clock means, and pre-scaler output means for indicating when said further counter means has counted a prescribed number of clock signals.
Claim 10
Dependent Claim
26 words
The synchronizer circuit recited in claim 8 wherein, said pre-scaler output means includes flip-flop means connected to pipeline the count condition of said further counter means.
Claim 11
Dependent Claim
103 words
The synchronizer circuit recited in claim 1 wherein; said divider means includes input storage latches connected to said control means and adapted to store a prescribed division value, a plurality of flip-flop means which are connected to said input storage latches in order to operate as a down counter, and to supply an enable signal to said clock means to control the operation thereof, and logic circuit means connected between said input storage means and said plurality of flip-flop means to modify the division value stored in said input storage means in response to a lead or lag signal from said detector means.
Claim 12
Dependent Claim
27 words
The synchronizer circuit recited in claim 10 wherein, said divider means further includes count storage means connected to said counter means to store a lead/lag count signal.
Claim 13
Dependent Claim
21 words
The synchronizer recited in claim 1 including, master clock signal supplying means for supplying master clock signals to said clock means.
Claim 14
Dependent Claim
22 words
The synchronizer recited in claim 12 wherein, said master clock signal supplying means provides a plurality of clock signals having different frequencies.
Claim 15
Dependent Claim
61 words
The synchronizer circuit recited in claim 1 wherein, said counter means includes up/down counter means connected to receive signals from said detector means and to supply a lead signal or a lag signal to said divider means to indicate that the input signals respectively lead or lag the clock signals and to selectively alter the division factor of said divider means.
Claim 16
Dependent Claim
18 words
The synchronizer circuit recited in claim 1 wherein, said control means includes a microprocessor controller and bus means.
Claim 17
Dependent Claim
43 words
The synchronizer recited in claim 1 including, clock counter means (23) connected to receive clock signals from said clock means and control signals from said control means and operative to produce a synchronous clock signal with a divided-down representation of said clock signals.
Claim 18
Dependent Claim
28 words
The synchronizer circuit recited in claim 16 wherein, said clock counter means includes preloaded counters and is connected to supply said divided-down clock signals to said pre-scaler means.
Claim 19
Dependent Claim
52 words
The synchronizer circuit recited in claim 17 wherein, said clock counter means includes input latch storage means connected to receive signals from said control means thereby to determine the divided down factor, and counting circuit means connected to said input latch storage means to count in accordance with said divided down factor.
Claim 20
Dependent Claim
35 words
The synchronizer circuit recited in claim 16 wherein, said sync lock circuit means includes fast sync means for synchronizing said input signals and said clock signals by selectively supplying signals to said clock counter means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-03-23 | 1990-09-22 | 1991-03-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-03-23 | 1994-09-22 | 1995-03-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-03-23 | 1998-09-22 | 1999-03-24 | $7700.00 | Window Closed / Lapsed |