NPN transistor with P/N closed loop in contact with collector electrode

Claim 1

A semiconductor device comprising: a p-type semiconductor substrate; an n-type semiconductor layer formed on the upper surface of said p-type semiconductor substrate; a p-type isolation diffusion layer formed to extend from the upper surface of said p-type semiconductor substrate to the upper surface of said n-type semiconductor layer to form an n-type collector region in said n-type semiconductor layer which is isolated by said p-type isolation diffusion layer; a p-type base region formed in an upper surface of said n-type collector region; an n-type emitter region formed in an upper surface of said base region; a p-type impurity region formed in an upper surface of said n-type collector region between said p-type base region and said p-type isolation layer, said p-type impurity region substantially surrounding said p-type base region and forming an open loop; a high concentration n-type region for forming a collector electrode in the upper surface of said n-type collector region, said high concentration n-type region contacting said p-type impurity region to close said open loop such that said n-type region and said p-type impurity region form a closed loop, said high concentration n-type region not comprising a portion of any high concentration n-type closed loop surrounding said p-type base region; and a collector electrode formed in contact with both said p-type impurity region and said high concentration n-type region.