Patent US4652832A successfully refreshed from Google Patents.
US4652832A
Expired / Lapsed
US
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Frequency resolution in a digital oscillator
Assignee: Motorola Solutions Inc
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Filing: 1985-07-05
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Granted: 1987-03-24
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Expires: 2005-07-05
Abstract
Abstract A method and means for improving the frequency resolution in a digital oscillator is described. According to the principles of the present invention, a digital oscillator may be comprised of a frequency latch, a phase accumulator, and a ROM based waveform generator. Improved frequency resolution is achieved in the digital oscillator, without increasing ROM size by quantizing the summed output of a dither generator and the phase accumulator before sending the resultant multi-bit signal to a ROM. The contents of the ROM are sequentially addressed with the resultant multi-bit signal. The output of the ROMs comprise digital words corresponding to a desired waveform envelope.
Inventors
- 👤 Steven C. Jasper
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 15:13
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/02; G06F1/03; G06F1/0321; G06F1/0342; G06F2211/00; G06F2211/902
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
138 words
A digital oscillator having improved frequency resolution, said digital oscillator comprising: (a) latching means for inputting a binary signal which indicates the desired operating frequency for the digital oscillator; (b) phase accumulator means coupled to said latching means for generating a sequence of binary words, representing phase, corresponding to the desired operating frequency for the digital oscillator; (c) dither generator means for generating a signal comprising random digital noise; (d) digital summation means for combining the respective outputs of said phase accumulator means and said digital dither generator means; (e) truncating means for selecting the most significant portion of the output of said digital summation means; and (f) direct ROM look-up means, coupled to the output of said truncating means, for producing a sequential digital signal which corresponds to an oscillating sinusoidal signal of said desired operating frequency.
Claim 2
Dependent Claim
138 words
A digital oscillator having improved frequency resolution, said digital oscillator comprising: (a) latching means for inputting a binary signal which indicates the desired operating frequency for the digital oscillator; (b) phase accumulator means coupled to said latching means for generating a sequence of binary words, representing phase, corresponding to the desired operating frequency for the digital oscillator; (c) dither generator means for generating a signal comprising random digital noise; (d) digital summation means for combining the respective outputs of said phase accumulator means and said digital dither generator means; (e) truncating means for selecting the most significant portion of the output of said digital summation means; and (f) direct ROM look-up means, coupled to the output of said truncating means, for producing a sequential digital signal which corresponds to an oscillating sinusoidal signal of said desired operating frequency.
Claim 3
Independent Claim
122 words
A method for improving frequency resolution in a digital oscillator, said method comprising the steps of: (a) inputting a binary signal which indicates the desired operating frequency for the digital oscillator; (b) generating a sequence of binary words, representing phase, corresponding to the desired operating frequency for the digital oscillator; (c) generating a digital dither signal comprising random digital noise; (d) summing the respective generated phase words and digital dither words; (e) selecting the most significant portion of the summed digital phase and dither words; and (f) producing a sequential digital signal which corresponds to an oscillating sinusoidal signal of said desired frequency, by addressing a ROM lookup means with said selected significant portion of said combined digital phase and dither words.
Claim 4
Independent Claim
122 words
A method for improving frequency resolution in a digital oscillator, said method comprising the steps of: (a) inputting a binary signal which indicates the desired operating frequency for the digital oscillator; (b) generating a sequence of binary words, representing phase, corresponding to the desired operating frequency for the digital oscillator; (c) generating a digital dither signal comprising random digital noise; (d) summing the respective generated phase words and digital dither words; (e) selecting the most significant portion of the summed digital phase and dither words; and (f) producing a sequential digital signal which corresponds to an oscillating sinusoidal signal of said desired frequency, by addressing a ROM lookup means with said selected significant portion of said combined digital phase and dither words.
Claim 5
Independent Claim
123 words
A method for improving frequency resolution in a digital oscillator, said method comprising the steps of: (a) inputting a binary signal which indicates the desired operating frequency for the digital oscillator; (b) generating a sequence of binary words, representing phase, corresponding to the desired operating frequency for the digital oscillator; (c) generating a digital dither signal comprising random digital noise; (d) summing the respective generated phase words and digital dither words; (e) selecting the most significant portion of the summed digital phase and dither words; and (f) producing a sequential digital signal which corresponds to an oscillating sinusoidal signal of said desired frequency, by addressing a factored ROM lookup means with said selected significant portion of said combined digital phase and dither words.
Claim 6
Independent Claim
123 words
A method for improving frequency resolution in a digital oscillator, said method comprising the steps of: (a) inputting a binary signal which indicates the desired operating frequency for the digital oscillator; (b) generating a sequence of binary words, representing phase, corresponding to the desired operating frequency for the digital oscillator; (c) generating a digital dither signal comprising random digital noise; (d) summing the respective generated phase words and digital dither words; (e) selecting the most significant portion of the summed digital phase and dither words; and (f) producing a sequential digital signal which corresponds to an oscillating sinusoidal signal of said desired frequency, by addressing a factored ROM lookup means with said selected significant portion of said combined digital phase and dither words.
Claim 7
Dependent Claim
138 words
A digital oscillator having improved frequency resolution, said digital oscillator comprising: (a) latching means for inputting a binary signal which indicates the desired operating frequency for the digital oscillator; (b) phase accumulator means coupled to said latching means for generating a sequence of binary words, representing phase, corresponding to the desired operating frequency for the digital oscillator; (c) dither generator means for generating a signal comprising random digital noise; (d) digital summation means for combining the respective outputs of said phase accumulator means and said digital dither generator means; (e) truncating means for selecting the most significant portion of the output of said digital summation means; and (f) factored ROM look-up means, coupled to the output of said truncating means, for producing a sequential digital signal which corresponds to an oscillating sinusoidal signal of said desired operating frequency.
Claim 8
Dependent Claim
138 words
A digital oscillator having improved frequency resolution, said digital oscillator comprising: (a) latching means for inputting a binary signal which indicates the desired operating frequency for the digital oscillator; (b) phase accumulator means coupled to said latching means for generating a sequence of binary words, representing phase, corresponding to the desired operating frequency for the digital oscillator; (c) dither generator means for generating a signal comprising random digital noise; (d) digital summation means for combining the respective outputs of said phase accumulator means and said digital dither generator means; (e) truncating means for selecting the most significant portion of the output of said digital summation means; and (f) factored ROM look-up means, coupled to the output of said truncating means, for producing a sequential digital signal which corresponds to an oscillating sinusoidal signal of said desired operating frequency.
Claim 9
Dependent Claim
20 words
The improved digital oscillator of claim 1 or 4, wherein said phase accumulator means has a length of N bits.
Claim 10
Dependent Claim
9 words
The improved digital oscillator of claim 5, wherein N=20.
Claim 11
Dependent Claim
21 words
The improved digital oscillator of claim 1 or 4, wherein said dither signal comprises an L bit random digital noise signal.
Claim 12
Dependent Claim
9 words
The improved digital oscillator of claim 7, wherein L=3.
Claim 13
Dependent Claim
19 words
The improved digital oscillator of claim 1 or 4, wherein said truncating means has a length of M bits.
Claim 14
Dependent Claim
9 words
The improved digital oscillator of claim 9, wherein M=17.
Claim 15
Dependent Claim
18 words
The improved digital oscillator of claim 1 or 4, wherein said dither signal has a uniform probability density.
Claim 16
Dependent Claim
21 words
The improved digital oscillator of claim 1 or 4, wherein dither generator means comprises a feeback shift register pseudorandom sequence generator.
Claim 17
Dependent Claim
18 words
The improved digital oscillator of claim 12, wherein said feedback shift register has a length of 10 bits.
Claim 18
Dependent Claim
23 words
The improved digital oscillator of claim 1 or 4, wherein the length of said latching means and said phaae accumulator means are equal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-03-23 | 1990-09-22 | 1991-03-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-03-23 | 1994-09-22 | 1995-03-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-03-23 | 1998-09-22 | 1999-03-24 | $7700.00 | Window Closed / Lapsed |