Semiconductor memory device having stacked capacitor-type memory cells

Claim 1

A semiconductor memory device comprising: a semiconductor substrate of a first conductivity type; a plurality of word lines made of a first conductive layer extending on said substrate and insulated therefrom; a plurality of bit lines made of a second conductive layer, said bit lines intersecting said word lines and being insulated therefrom; and stacked capacitor-type memory cells formed in the vicinity of respective intersections between said word lines and bit lines, to define an array of memory cells, wherein each of said memory cells comprises first and second impurity doped regions of a second conductivity type opposite to said first conductivity type formed in said substrate, each said first impurity doped region being electrically connected to a respective one of said bit lines, said first and second impurity doped regions and a respective portion of a respective one of said word lines forming a transfer transistor, a third conductive layer electrically connected to said second impurity doped region, for forming one of two capacitor electodes wherein, for a memory cell at the interior of said array, said third conductive layer has a portion which overlaps, without contact, with a respective portion of the respective third conductive layer of an adjacent memory cell, so that the respective overlapping parts of the third conductive layers of the adjoining memory cells are at different levels, an insulating layer disposed on said third conductive layer to provide the dielectric of said capacitor, a fourth conductive layer, disposed on said insulating layer, for forming the other of said two capacitor electrodes, and said respective bit lines extending over and being insulated from said fourth conductive layer.