Adaptive delta modulation codec

Claim 2

A syllabic filter for changing the amplitude of a voice approximation signal provided by a continuously variable slope delta modulation (CVSD) codec in each sample interval, by an amount proportional to a difference magnitude between the voice approximation signal and an actual voice signal received by the codec, as indicated by the coincidence of a first logic state of a coincidence signal bit provided by the codec in successive sample intervals, the filter comprising: counter means, responsive to the coincidence signal bit and to a binary rate signal bit, for providing a syllabic signal having a syllabic count in each sample interval between a minimum count, corresponding to low coincidence of the coincidence bit first logic state, and a maximum count corresponding to a high coincidence thereof, said syllabic count increasing by one in the presence of the coincidence signal bit first logic state and decreasing by one in the presence of a first logic state of said binary rate signal bit, said count remaining constant in the simultaneous presence and, alternately, in the simultaneous absence of the coincidence signal bit first logic state and said binary rate signal bit first logic state; binary rate multiplier means, for providing said binary rate signal bit first logic state to said counter means, periodically, at a variable frequency which increases with an increasing syllabic count value; signal decode means, for decoding said syllabic count into first and second state signals in each sample interval, said first state signal identifying a highest whole range exceeded by said syllabic count from among a plurality of sequential, equal increment syllabic count value ranges between said minimum value and said maximum value, said second state signal identifying the incremental syllabic count value above the highest whole range identified by said first state signal; first converter means, for providing a first analog signal in each sample interval at an amplitude proportional to said highest whole range identified by said first state signal, said first converter means increasing said first analog signal amplitude, non-linearly, in increasingly greater magnitude increments and, alternately, decreasing said first analog signal amplitude in increasingly lesser magnitude increments, in succeeding sample intervals, in response to said first state signal indicating a highest whole range which is higher or lower, respectively, in said sequence of value ranges; second converter means, for providing a second analog signal in each sample period at an amplitude proportional to said incremental syllabic count value identified by said second state signal, and for changing said second analog signal amplitude linearly, upward and downward, in response to said second state signal indicating a higher syllabic count value and a lower syllabic count value, respectively; and integrator means, for adding said first analog signal amplitude to said second analog signal amplitude in each sample period period, to provide the sum signal amplitude thereof as the codec voice approximation signal amplitude.

Claim 3

The syllabic filter of claim 1, further comprising: synchronization circuit means, responsive to the coincidence signal bit and to a codec clock signal, for providing a synchronization reset signal to said binary rate multiplier to periodically reset the output thereof in response to the presence of the first logic state of the coincidence signal bit in consecutive sample intervals.

Claim 4

A continuously variable slope delta modulation (CVSD) encoder, for providing adaptive delta modulation (ADM) encoding of a received analog voice signal into a series ADM signal having a binary ADM sample bit in each of successive sample intervals of the encoder, comprising: comparator means, for comparing the received analog voice signal amplitude with that of a voice approximation signal, to provide each ADM sample bit in a first logic state and, alternately, in a second logic state in response to said approximation signal being greater than or less than the received analog voice signal; coincidence detector means, responsive to each ADM sample bit for detecting reoccurrence of a same ADM logic state in successive sample intervals, and for presenting a coincidence signal bit in a first logic state on each said reoccurrence; syllabic filter means, including counter means, responsive to the coincidence signal bit and to a binary rate signal bit, for providing a syllabic signal having a syllabic count in each sample interval between a minimum count, corresponding to low coincidence of the coincidence bit first logic state, and a maximum count corresponding to a high coincidence thereof, said syllabic count increasing by one in the presence of the coincidence signal bit first logic state and decreasing by one in the presence of a first logic state of said binary rate signal bit, said count remaining constant in the simultaneous presence and, alternately, in the simultaneous absence of the coincidence signal bit first logic state and said binary rate signal bit first logic state; binary rate multiplier means, for providing said binary rate signal bit first logic state to said counter means, periodically, at a variable frequency which increases with an increasing syllabic count value; signal decode means, for decoding said syllabic count into first and second state signals in each sample interval, said first state signal identifying the highest whole range exceeded by said syllabic count from among a plurality of sequential, equal increment syllabic count value ranges between said minimum value and said maximum value, said second state signal identifying the incremental syllabic count value above the highest whole range identified by said first state signal; first converter means, for providing a first analog signal in each sample interval at an amplitude proportional to said highest whole range identified by said first state signal, said first converter means increasing said first analog signal amplitude, nonlinearly, in increasingly greater magnitude increments and, alternately, decreasing said first analog signal amplitude in increasingly lesser magnitude increments, in succeeding sample intervals, in response to said first state signal indicating a highest whole range which is higher or lower, respectively, in said sequence of value ranges; second converter means, for providing a second analog signal in each sample period at an amplitude proportional to said incremental syllabic count value identified by said second state signal, and for changing said second analog signal amplitude linearly, upward and downward, in response to said second state signal indicating a higher syllabic count value and a lower syllabic count value, respectively; and integrator means, for adding said first analog signal amplitude to said second analog signal amplitude in each sample period period, to provide the sum signal amplitude thereof as said voice approximation signal amplitude.

Claim 5

A continuously variable slope delta modulation (CVSD) encoder, for providing adaptive delta modulation (ADM) encoding of a received analog voice signal into a series ADM signal having a binary ADM sample bit in each of successive sample intervals of the encoder, comprising: comparator means, for comparing the received analog voice signal amplitude with that of a voice approximation signal, to provide each ADM sample bit in a first logic state and, alternately, in a second logic state in response to said approximation signal being greater than or less than the received analog voice signal; coincidence detector means, responsive to each ADM sample bit for detecting reoccurrence of a same ADM logic state in successive sample intervals, and for presenting a coincidence signal bit in a first logic state on each said reoccurrence; syllabic filter means, including counter means, responsive to the coincidence signal bit and to a binary rate signal bit, for providing a syllabic signal having a syllabic count in each sample interval between a minimum count, corresponding to low coincidence of the coincidence bit first logic state, and a maximum count corresponding to a high coincidence thereof, said syllabic count increasing by one in the presence of the coincidence signal bit first logic state and decreasing by one in the presence of a first logic state of said binary rate signal bit, said count remaining constant in the simultaneous presence and, alternately, in the simultaneous absence of the coincidence signal bit first logic state and said binary rate signal bit first logic state; binary rate multiplier means, for providing said binary rate signal bit first logic state to said counter means, periodically, at a variable frequency which increases with an increasing syllabic count value; signal decode means, for decoding said syllabic count into first and second state signals in each sample interval, said first state signal identifying the highest whole range exceeded by said syllabic count from among a plurality of sequential, equal increment syllabic count value ranges between said minimum value and said maximum value, said second state signal identifying the incremental syllabic count value above the highest whole range identified by said first state signal; first converter means, for providing a first analog signal in each sample interval at an amplitude proportional to said highest whole range identified by said first state signal, said first converter means increasing said first analog signal amplitude, nonlinearly, in increasingly greater magnitude increments and, alternately, decreasing said first analog signal amplitude in increasingly lesser magnitude increments, in succeeding sample intervals, in response to said first state signal indicating a highest whole range which is higher or lower, respectively, in said sequence of value ranges; second converter means, for providing a second analog signal in each sample period at an amplitude proportional to said incremental syllabic count value identified by said second state signal, and for changing said second analog signal amplitude linearly, upward and downward, in response to said second state signal indicating a higher syllabic count value and a lower syllabic count value, respectively; and integrator means, for adding said first analog signal amplitude to said second analog signal amplitude in each sample period period, to provide the sum signal amplitude thereof as said voice approximation signal amplitude.

Claim 6

The encoder of claim 3, further comprising: synchronization circuit means, responsive to the coincidence signal bit and to an encoder clock signal, for providing a synchronization reset signal to said binary rate multiplier to periodically reset the output thereof in response to the presence of the first logic state of the coincidence signal bit in consecutive sample intervals.