Serial-parallel data transfer system for VLSI data paths

Claim 1

Apparatus for transferring a multi-bit data word from a source functional unit to a destination functional unit, said units being two of a plurality of functional units on the same semiconductor chip, each said unit having a unique address, said apparatus comprising: a plurality of multi-stage registers, each such register coupled to a respective one of said units, said registers transferring said data in parallel to and from said units, said registers located on said chip and serially connected to each other with the input to the first register coupled to the output of the last register to form a closed loop serial data path; control means coupled to said registers and responsive to the addresses of said source and destination functional units for providing control signals to sequentially cause a parallel transfer of said data word from said source unit to its respective multi-stage register, a shifting of said data word through said registers in a manner to move said data word to the respective register of said destination unit, and a parallel transfer of said data word to said destination unit; wherein said control means includes: modulus m counting means for counting the bit displacement of said data word while said data word is shifted through said registers of said data path; and a controller coupled to said counting means for providing said control signals to said registers and for determining the number of shifts necessary to transfer said data word from said respective multi-stage register of said source unit to said respective multi-stage register of said destination unit by presetting said counting means to said source address and incrementing said counting means upon each shift of one bit of said data word until the count of said counting means is equal to said destination address whereupon said data word has been shifted the necessary number of bits to move said data word from said respective multi-stage register of said source unit to said respective multi-stage register of said destination unit.

Claim 5

A method for serially transferring data between a multiplicity of functional units of a semiconductor chip, wherein said chip includes a plurality of data registers serially connected to each other with the input to the first register coupled to the output of the last register to form a closed loop serial data path with each register coupled to a respective one of said functional units, and wherein said registers include parallel data ports for transferring data to and from their respective functional units, said chip further including means for controlling the operation of said registers and modulus m counting means coupled to said controlling means wherein m is equal to the total number of bits in said serial data path, said method comprising the steps of: (a) assigning a unique address to each of said registers, said address corresponding to a digital value which represents the number of data bits from a fixed bit within said serial data path to the last bit of the register to be addresed, counting in the direction of serial data flow; (b) latching first and second addresses into said controlling means, said first and second addresses corresponding to the respective address of a source register and a destination register; (c) presetting the count of said counting means with said first address; (d) transferring the data to said source register from its respective source unit; (e) serially shifting said data one bit in said data path; (f) incrementing said count by one; (g) comparing said count to said second address for equality; (h) repeating steps e-g if said count is not equal to said second address; and (i) transferring said data to the respective functional unit of said destination register when said count variable is equal to the address of said destination unit.

Claim 6

A method for serially transferring data between a multiplicity of functional units of a semiconductor chip, wherein said chip includes a plurality of data registers serially connected to each other with the input to the first register coupled to the output of the last register to form a closed loop serial data path with each register coupled to a respective one of said functional units, and wherein said registers include parallel data ports for transferring data to and from their respective functional units, said chip further including means for controlling the operation of said registers and modulus m counting means coupled to said controlling means wherein m is equal to the total number of bits in said serial data path, said method comprising the steps of: (a) assigning a unique address to each of said registers, said address corresponding to a digital value which represents the number of data bits from a fixed bit within said serial data path to the last bit of the register to be addresed, counting in the direction of serial data flow; (b) latching first and second addresses into said controlling means, said first and second addresses corresponding to the respective address of a source register and a destination register; (c) presetting the count of said counting means with said first address; (d) transferring the data to said source register from its respective source unit; (e) serially shifting said data one bit in said data path; (f) incrementing said count by one; (g) comparing said count to said second address for equality; (h) repeating steps e-g if said count is not equal to said second address; and (i) transferring said data to the respective functional unit of said destination register when said count variable is equal to the address of said destination unit.