US4438491A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Computer having plural IC chips with each chip including a transceiver
Assignee: Advanced Micro Devices Inc
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Filing: 1980-10-14
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Granted: 1984-03-20
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Expires: 2000-10-14
Abstract
Abstract A computer having a plurality of interconnected IC chips. Chips include a transceiver for sending and receiving signals from other chips. By implementing on-chip transceivers, the communication between chips in the computer is done with fewer wires.
Inventors
- 👤 James N. Constant
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 12:30
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/22
Claims Analysis
Total Claims: 41
Claim 1
Independent Claim
140 words
In a computer with monolithic IC chips interconnected for data transfers, the improvement to reduce the number of interconnections between chips including: at least some IC chips with a first chip area devoted to one or more logic circuits, a second chip area devoted to interfacing means, and a third chip area devoted to at least one of a transmitter and receiver connected between said logic circuits and said interfacing means, said interfacing means comprising one or more pads each connected to a conductor for carrying analog signals for interconnecting said IC chips, said transmitter for receiving first signals from said logic circuits and providing second signals to said interfacing means, and said receiver for receiving third signals from said interfacing means and providing fourth signals to said logic circuits, said transmitter and receiver including means for handling analog signals.
Claim 2
Dependent Claim
140 words
In a computer with monolithic IC chips interconnected for data transfers, the improvement to reduce the number of interconnections between chips including: at least some IC chips with a first chip area devoted to one or more logic circuits, a second chip area devoted to interfacing means, and a third chip area devoted to at least one of a transmitter and receiver connected between said logic circuits and said interfacing means, said interfacing means comprising one or more pads each connected to a conductor for carrying analog signals for interconnecting said IC chips, said transmitter for receiving first signals from said logic circuits and providing second signals to said interfacing means, and said receiver for receiving third signals from said interfacing means and providing fourth signals to said logic circuits, said transmitter and receiver including means for handling analog signals.
Claim 3
Dependent Claim
13 words
The computer of claim 1 wherein the computer is a general purpose computer.
Claim 4
Dependent Claim
12 words
The computer of claim 1 wherein some IC chips are memory chips.
Claim 5
Dependent Claim
16 words
The computer of claim 1 including electromagnetic means for interconnecting at least some of said chips.
Claim 6
Dependent Claim
16 words
The computer of claim 1 including optical means for interconnecting at least some of said chips.
Claim 7
Dependent Claim
19 words
The computer of claim 1 wherein said transmitter includes a light emitting diode and said receiver is a photodetector.
Claim 8
Dependent Claim
22 words
The computer of claim 1 wherein at least one of said first and fourth signals are one of analog or digital signals.
Claim 9
Independent Claim
130 words
The method of reducing interconnections between interconnected monolithic IC chips in a computer, including the steps of: providing at least some IC chips with a first chip area devoted to one or more logic circuits, a second chip area devoted to interfacing means, and a third chip area devoted to at least one of a transmitter and receiver connected between said logic circuits and said interfacing means; interconnecting said IC chips with analog signals through said interfacing means comprising one or more pads connected to a conductor; inputting first signals from said logic circuits to the transmitter and providing second signals from the transmitter to said interfacing means; and, inputting third signals from said interfacing means to the receiver and providing fourth signals from the receiver to said logic circuits.
Claim 10
Independent Claim
130 words
The method of reducing interconnections between interconnected monolithic IC chips in a computer, including the steps of: providing at least some IC chips with a first chip area devoted to one or more logic circuits, a second chip area devoted to interfacing means, and a third chip area devoted to at least one of a transmitter and receiver connected between said logic circuits and said interfacing means; interconnecting said IC chips with analog signals through said interfacing means comprising one or more pads connected to a conductor; inputting first signals from said logic circuits to the transmitter and providing second signals from the transmitter to said interfacing means; and, inputting third signals from said interfacing means to the receiver and providing fourth signals from the receiver to said logic circuits.
Claim 11
Dependent Claim
17 words
The method of claim 8 including the step of implementing the computer as a special purpose computer.
Claim 12
Dependent Claim
13 words
The method of claim 8 including the step of providing a multiplier chip.
Claim 13
Dependent Claim
23 words
The method of claim 8 including the step of providing the transmitter as a light emitting diode, and the receiver as a photodetector.
Claim 14
Dependent Claim
23 words
The method of claim 8 including the steps of providing at least one of the transmitter, receiver and interfacing means as electrical means.
Claim 15
Dependent Claim
16 words
The method of claim 8 including the step of interconnecting some IC chips with optical means.
Claim 16
Dependent Claim
16 words
The method of claim 4 including the step of interconnecting some IC chips with acoustical means.
Claim 17
Dependent Claim
16 words
The method of claim 8 including the step of interconnecting some IC chips with electromagnetic means.
Claim 18
Dependent Claim
23 words
The method of claim 8 including utilizing at least one of said first and fourth signals in one of analog or digital form.
Claim 19
Dependent Claim
15 words
The method of claim 8 including producing analog signals at a third chip area transmitter.
Claim 20
Dependent Claim
147 words
In a computer with monolithic IC chips interconnected for data transfers, the improvement to reduce the number of interconnections between chips including: at least some IC chips with a first chip area devoted to one or more logic circuits, a second chip area devoted to interfacing means, and a third chip area devoted to at least one of a transmitter and receiver connected between said logic circuits and said interfacing means, said interfacing means comprising one or more pads each connected to a conductor for interconnecting said IC chips, said transmitter for receiving first signals from said logic circuits and providing second signals to said interfacing means, and said receiver for receiving third signals from said interfacing means and providing fourth signals to said logic circuits, with at least one of said transmitter and receiver incorporating signal processing means for processing the corresponding one of said signals.
Claim 21
Dependent Claim
147 words
In a computer with monolithic IC chips interconnected for data transfers, the improvement to reduce the number of interconnections between chips including: at least some IC chips with a first chip area devoted to one or more logic circuits, a second chip area devoted to interfacing means, and a third chip area devoted to at least one of a transmitter and receiver connected between said logic circuits and said interfacing means, said interfacing means comprising one or more pads each connected to a conductor for interconnecting said IC chips, said transmitter for receiving first signals from said logic circuits and providing second signals to said interfacing means, and said receiver for receiving third signals from said interfacing means and providing fourth signals to said logic circuits, with at least one of said transmitter and receiver incorporating signal processing means for processing the corresponding one of said signals.
Claim 22
Dependent Claim
13 words
The computer of claim 18 wherein said signal processing means includes a modem.
Claim 23
Dependent Claim
13 words
The computer of claim 18 wherein said signal processing means includes a codec.
Claim 24
Dependent Claim
17 words
The computer of claim 18 wherein said signal processing means includes one of sampling and desampling means.
Claim 25
Dependent Claim
17 words
The computer of claim 18 wherein said signal processing means includes one of multiplexing and demultiplexing means.
Claim 26
Dependent Claim
138 words
In a computer with monolithic IC chips interconnected for data transfers, the improvement to reduce the number of interconnections between chips including: at least some IC chips with a first chip area devoted to one or more logic circuits, a second chip area devoted to interfacing means, and a third chip area devoted to at least one of a transmitter and receiver connected between said logic circuits and said interfacing means, said interfacing means comprising one or more pads each connected to a conductor for interconnecting said IC chips, said transmitter for receiving first signals from said logic circuits and providing second signals to said interfacing means, and said receiver for receiving third signals from said interfacing means and providing fourth signals to said logic circuits, said transmitter and/or receiver including one of a D/A and A/D converter.
Claim 27
Dependent Claim
138 words
In a computer with monolithic IC chips interconnected for data transfers, the improvement to reduce the number of interconnections between chips including: at least some IC chips with a first chip area devoted to one or more logic circuits, a second chip area devoted to interfacing means, and a third chip area devoted to at least one of a transmitter and receiver connected between said logic circuits and said interfacing means, said interfacing means comprising one or more pads each connected to a conductor for interconnecting said IC chips, said transmitter for receiving first signals from said logic circuits and providing second signals to said interfacing means, and said receiver for receiving third signals from said interfacing means and providing fourth signals to said logic circuits, said transmitter and/or receiver including one of a D/A and A/D converter.
Claim 28
Dependent Claim
132 words
In a computer with monolithic IC chips interconnected for data transfers, the improvement to reduce the number of interconnections between chips including: at least some IC chips with a first chip area devoted to one or more logic circuits, a second chip area devoted to interfacing means, and a third chip area devoted to at least one of a transmitter and receiver connected between said logic circuits and said interfacing means, said interfacing means comprising one or more pads each connected to a conductor for interconnecting said IC chips, said transmitter including a modem for receiving first signals from said logic circuits and providing second signals to said interfacing means, and said receiver including an modem for receiving third signals from said interfacing means and providing fourth signals to said logic circuits.
Claim 29
Dependent Claim
132 words
In a computer with monolithic IC chips interconnected for data transfers, the improvement to reduce the number of interconnections between chips including: at least some IC chips with a first chip area devoted to one or more logic circuits, a second chip area devoted to interfacing means, and a third chip area devoted to at least one of a transmitter and receiver connected between said logic circuits and said interfacing means, said interfacing means comprising one or more pads each connected to a conductor for interconnecting said IC chips, said transmitter including a modem for receiving first signals from said logic circuits and providing second signals to said interfacing means, and said receiver including an modem for receiving third signals from said interfacing means and providing fourth signals to said logic circuits.
Claim 30
Dependent Claim
132 words
In a computer with monolithic IC chips interconnected for data transfers, the improvement to reduce the number of interconnections between chips including: at least some IC chips with a first chip area devoted to one or more logic circuits, a second chip area devoted to interfacing means, and a third chip area devoted to at least one of a transmitter and receiver connected between said logic circuits and said interfacing means, said interfacing means comprising one or more pads each connected to a conductor for interconnecting said IC chips, said transmitter including a codec for receiving first signals from said logic circuits and providing second signals to said interfacing means, and said receiver including a codec for receiving third signals from said interfacing means and providing fourth signals to said logic circuits.
Claim 31
Dependent Claim
132 words
In a computer with monolithic IC chips interconnected for data transfers, the improvement to reduce the number of interconnections between chips including: at least some IC chips with a first chip area devoted to one or more logic circuits, a second chip area devoted to interfacing means, and a third chip area devoted to at least one of a transmitter and receiver connected between said logic circuits and said interfacing means, said interfacing means comprising one or more pads each connected to a conductor for interconnecting said IC chips, said transmitter including a codec for receiving first signals from said logic circuits and providing second signals to said interfacing means, and said receiver including a codec for receiving third signals from said interfacing means and providing fourth signals to said logic circuits.
Claim 32
Dependent Claim
140 words
In a computer with monolithic IC chips interconnected for data transfers, the improvement to reduce the number of interconnections between chips including: at least some IC chips with a first chip area devoted to one or more logic circuits, a second chip area devoted to interfacing means, and a third chip area devoted to at least one of a transmitter and receiver connected between said logic circuits and said interfacing means, said interfacing means comprising one or more pads each connected to a conductor for interconnecting said IC chips, said transmitter for receiving first signals from said logic circuits and providing second signals to said interfacing means, and said receiver for receiving third signals from said interfacing means and providing fourth signals to said logic circuits, with at least one of said transmitter, receiver and interfacing means including optical means.
Claim 33
Dependent Claim
140 words
In a computer with monolithic IC chips interconnected for data transfers, the improvement to reduce the number of interconnections between chips including: at least some IC chips with a first chip area devoted to one or more logic circuits, a second chip area devoted to interfacing means, and a third chip area devoted to at least one of a transmitter and receiver connected between said logic circuits and said interfacing means, said interfacing means comprising one or more pads each connected to a conductor for interconnecting said IC chips, said transmitter for receiving first signals from said logic circuits and providing second signals to said interfacing means, and said receiver for receiving third signals from said interfacing means and providing fourth signals to said logic circuits, with at least one of said transmitter, receiver and interfacing means including optical means.
Claim 34
Dependent Claim
140 words
In a computer with monolithic IC chips interconnected for data transfers, the improvement to reduce the number of interconnections between chips including: at least some IC chips with a first chip area devoted to one or more logic circuits, a second chip area devoted to interfacing means, and a third chip area devoted to at least one of a transmitter and receiver connected between said logic circuits and said interfacing means, said interfacing means comprising one or more pads each connected to a conductor for interconnecting said IC chips, said transmitter for receiving first signals from said logic circuits and providing second signals to said interfacing means, and said receiver for receiving third signals from said interfacing means and providing fourth signals to said logic circuits, with at least one of said transmitter, receiver and interfacing means including acoustical means.
Claim 35
Dependent Claim
140 words
In a computer with monolithic IC chips interconnected for data transfers, the improvement to reduce the number of interconnections between chips including: at least some IC chips with a first chip area devoted to one or more logic circuits, a second chip area devoted to interfacing means, and a third chip area devoted to at least one of a transmitter and receiver connected between said logic circuits and said interfacing means, said interfacing means comprising one or more pads each connected to a conductor for interconnecting said IC chips, said transmitter for receiving first signals from said logic circuits and providing second signals to said interfacing means, and said receiver for receiving third signals from said interfacing means and providing fourth signals to said logic circuits, with at least one of said transmitter, receiver and interfacing means including acoustical means.
Claim 36
Dependent Claim
139 words
In a computer with monolithic IC chips interconnected for data transfers, the improvement to reduce the number of interconnections between chips including: at least one IC chip with a first chip area devoted to one or more logic circuits, a second chip area devoted to interfacing means, and a third chip area devoted to at least one of a transmitter and receiver connected between said logic circuits and said interfacing means, said interfacing means comprising one or more pads each connected to a conductor for interconnecting said IC chips, said transmitter for receiving first signals from said logic circuits and providing second signals to said interfacing means, and said receiver for receiving third signals from said interfacing means and providing fourth signals to said logic circuits, wherein at least one of said first and fourth signals are analog signals.
Claim 37
Dependent Claim
139 words
In a computer with monolithic IC chips interconnected for data transfers, the improvement to reduce the number of interconnections between chips including: at least one IC chip with a first chip area devoted to one or more logic circuits, a second chip area devoted to interfacing means, and a third chip area devoted to at least one of a transmitter and receiver connected between said logic circuits and said interfacing means, said interfacing means comprising one or more pads each connected to a conductor for interconnecting said IC chips, said transmitter for receiving first signals from said logic circuits and providing second signals to said interfacing means, and said receiver for receiving third signals from said interfacing means and providing fourth signals to said logic circuits, wherein at least one of said first and fourth signals are analog signals.
Claim 38
Independent Claim
142 words
The method of reducing interconnections between interconnected monolithic IC chips in a computer, including the steps of: providing at least some IC chips with a first chip area devoted to one or more logic circuits, a second chip area devoted to interfacing means, and a third chip area devoted to at least one of a transmitter and receiver connected between said logic circuits and said interfacing means; interconnecting said IC chips through said interfacing means comprising one or more pads connected to a conductor; inputting first signals from said logic circuits to the transmitter and providing second signals from the transmitter to said interfacing means; and, inputting third signals from said interfacing means to the receiver and providing fourth signals from the receiver to said logic circuit, including providing the transmitter with a light emitting diode and the receiver with a photodetector.
Claim 39
Independent Claim
142 words
The method of reducing interconnections between interconnected monolithic IC chips in a computer, including the steps of: providing at least some IC chips with a first chip area devoted to one or more logic circuits, a second chip area devoted to interfacing means, and a third chip area devoted to at least one of a transmitter and receiver connected between said logic circuits and said interfacing means; interconnecting said IC chips through said interfacing means comprising one or more pads connected to a conductor; inputting first signals from said logic circuits to the transmitter and providing second signals from the transmitter to said interfacing means; and, inputting third signals from said interfacing means to the receiver and providing fourth signals from the receiver to said logic circuit, including providing the transmitter with a light emitting diode and the receiver with a photodetector.
Claim 40
Independent Claim
142 words
The method of reducing interconnections between interconnected monolithic IC chips in a computer, including the steps of: providing at least some IC chips with a first chip area devoted to one or more logic circuits, a second chip area devoted to interfacing means, and a third chip area devoted to at least one of a transmitter and receiver connected between said logic circuits and said interfacing means; interconnecting said IC chips through said interfacing means comprising one or more pads connected to a conductor; inputting first signals from said logic circuits to the transmitter and providing second signals from the transmitter to said interfacing means; and, inputting third signals from said interfacing means to the receiver and providing fourth signals from the receiver to said logic circuit, including providing at least one of said transmitter, receiver and interfacing means with optical means.
Claim 41
Independent Claim
142 words
The method of reducing interconnections between interconnected monolithic IC chips in a computer, including the steps of: providing at least some IC chips with a first chip area devoted to one or more logic circuits, a second chip area devoted to interfacing means, and a third chip area devoted to at least one of a transmitter and receiver connected between said logic circuits and said interfacing means; interconnecting said IC chips through said interfacing means comprising one or more pads connected to a conductor; inputting first signals from said logic circuits to the transmitter and providing second signals from the transmitter to said interfacing means; and, inputting third signals from said interfacing means to the receiver and providing fourth signals from the receiver to said logic circuit, including providing at least one of said transmitter, receiver and interfacing means with optical means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-03-20 | 1987-09-19 | 1988-03-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-03-20 | 1991-09-19 | 1992-03-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-03-20 | 1995-09-19 | 1996-03-20 | $7700.00 | Window Closed / Lapsed |