US4362926A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Bus-register device for information processing
Assignee: V M E I LENIN
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Filing: 1979-10-19
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Granted: 1982-12-07
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Expires: 1999-10-19
Abstract
Abstract A register circuit for processing information in accordance with a given instruction set or set of transformation comprises N registers each having an input and an output and provided in a sequence R1, R2, R3, . . . RN, each register having n digits where N and n are integers. The output of the first register R1 is connected to a first bus while its input is connected to a second bus. All of the other registers R2, R3, . . . RN have their inputs connected to the first bus and their outputs to the second bus by respective strobe circuits. The strobe circuits of each of the buses R3 . . . RN are connected to respective control inputs a3 . . . aN. Additional control inputs a1 and a2 are connected to an OR-gate whose output is applied to the input strobe circuit of register R2 while the input a2 is also applied directly to the output strobe circuit of register R 2. This allows transfer of the contents of the first register to the second upon the application of a signal to the input a1 and parallel transfer between all the registers by the appropriate control inputs.
Inventors
- 👤 Lyudmil G. Dakovski
- 👤 Nikola K. Kassabov
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 22:22
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/30003; G06F9/30007; G06F9/30032; G05; G05B; G05B19/00; G05B19/02; G05B19/04; G05B19/07; G06F9/22; G06F9/223
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
395 words
An information processing device comprising: N, n-digit registers in a sequence R 1 , R 2 , R 3 , . . . R N , each of said registers having an input and an output; a respective input strobe circuit connected to the input of each register of said sequence from the second register R 2 to the last register R N thereof, and a respective output strobe circuit connected to the output of each register of said sequence from the second register R 2 to the last register R N thereof; a first information bus connected directly to the output of said first register R 1 and to each of the input strobe circuits, and a second information bus connected directly to the input of said first register R 1 of the sequence and to each of said output strobe circuits, each of said input strobe circuits transferring information signals to the respective register R 2 . . . R N from said first bus and each of said output strobe circuits transferring information signals from the respective registers R 2 . . . R N to said second bus upon the application of a control signal to a respective control input of the respective strobe circuit; respective first control lines to each of said registers of said sequence from the third register R 3 to the last register R N of said sequence, each of said first control lines being connected to the control inputs of both the input and output strobe circuits of the respective register R 3 . . . R N for direct control of transfer of information to and from the registers R 3 . . . R N ; a second control line connected directly to the control input of the output strobe circuit of the second register R 2 ; an OR-gate having its output connected to the control input of the input strobe circuit of the second register R 2 and a first input connected to said second control line; and a third control line connected to a second input of said OR-gate whereby a signal applied to said third control line transfers the contents of said first register R 1 to said second register R 2 through said buses and signals applied to the respective lines effect parallel transfer of information between said registers.
Claim 2
Dependent Claim
395 words
An information processing device comprising: N, n-digit registers in a sequence R 1 , R 2 , R 3 , . . . R N , each of said registers having an input and an output; a respective input strobe circuit connected to the input of each register of said sequence from the second register R 2 to the last register R N thereof, and a respective output strobe circuit connected to the output of each register of said sequence from the second register R 2 to the last register R N thereof; a first information bus connected directly to the output of said first register R 1 and to each of the input strobe circuits, and a second information bus connected directly to the input of said first register R 1 of the sequence and to each of said output strobe circuits, each of said input strobe circuits transferring information signals to the respective register R 2 . . . R N from said first bus and each of said output strobe circuits transferring information signals from the respective registers R 2 . . . R N to said second bus upon the application of a control signal to a respective control input of the respective strobe circuit; respective first control lines to each of said registers of said sequence from the third register R 3 to the last register R N of said sequence, each of said first control lines being connected to the control inputs of both the input and output strobe circuits of the respective register R 3 . . . R N for direct control of transfer of information to and from the registers R 3 . . . R N ; a second control line connected directly to the control input of the output strobe circuit of the second register R 2 ; an OR-gate having its output connected to the control input of the input strobe circuit of the second register R 2 and a first input connected to said second control line; and a third control line connected to a second input of said OR-gate whereby a signal applied to said third control line transfers the contents of said first register R 1 to said second register R 2 through said buses and signals applied to the respective lines effect parallel transfer of information between said registers.
References Cited (Backward Citations)
US3548167A
Cited
US3511977A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-12-06 | 1986-06-07 | 1986-12-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-12-06 | 1990-06-07 | 1990-12-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-12-06 | 1994-06-07 | 1994-12-07 | $7700.00 | Window Closed / Lapsed |