Didon digital demodulator

Claim 2

A DIDON digital demodulator comprising: analog-to-digital conversion means for (a) receiving a DIDON television video signal having a progressive variation and (b) delivering successive inter-sample signals at the frequency n×FB, n being a positive whole number at least equal to 4 and FB being a binary frequency of the DIDON signal, said successive inter-sample signals being representative of the progressive variation of said video signal from one sampling period to the next; identifying means for (a) identifying as a function of pre-established criteria configurations of n successive inter-sample signals which are probable configurations representative of a DIDON signal and (b) delivering (b1) auxiliary signals which indicate whether or not a configuration is identified as being representative of a DIDON signal, (b2) configuration signals which correspond to low-high "+" and high-low "-" transitions, and to high and low stable states of the DIDON signal; and data-regenerating means for receiving the configuration signals and regenerating a data signal and a clock signal when the configurations corresponding to said configuration signals are probable configurations representative of a DIDON signal.

Claim 3

A demodulator according to claim 1, wherein said conversion means includes: an analog-to-digital converter for supplying video-signal samples at the frequency n×FB; substractive means for supplying at the frequency n×FB subtractive signals which are representative of the difference between the samples delivered by the converter and the same samples delayed by 1, and n×FB scanning memory means for receiving the substractive signals, said memory means being programmed for delivering an inter-sample signal comprising a signal having a zero difference for a subtractive signal which is lower at absolute value than a predetermined threshold, and a signal having a difference + or - according to the sign of the subtractive signal if said subtractive signal is higher than the given threshold at absolute value.

Claim 4

A DIDON demodulator according to claim 2, wherein said identifying means include: register means for receiving the difference signals and for delivering at the frequency n.FB a window signal formed by the n last difference signals received; memory means being provided with a control input; and study means for (a) producing the configuration signals as a function of the pre-established criteria, (b) producing auxiliary signals, said auxiliary signals comprising a first signal for identifying improbable configurations, that is configurations which have been identified as being representative of no DIDON signal, and a second signal for identifying a leading-edge transition of a synchronization signal and for identifying a transition of a same type as the leading-edge transition, that is a low-high or a high-low transition according to whether said leading edge transition is a low-high or a high-low transition; an electronic switch controlled by the first signal, one output of said switch being connected to a control input of the memory means for delivering a signal at the frequency FB or a signal at the frequency n×FB according to whether the first signal corresponds to a probable configuration or not.

Claim 5

A DIDON demodulator according to claim 3, wherein the data-regenerating means includes: a signal input for receiving the configuration signals; and an input for receiving from said electronic switch the signal at the frequency n×FB and no signal at all respectively when the first signal corresponds to a probable configuration or to an improbable configuration, said data regenerating means providing a regenerated data signal having a time-duration 1/FD when the configuration is probable and presenting four different values respectively corresponding to whether the configuration is a "+" transition, a "-" transition, a low stable-state or a high stable-state, said data regeneration means also providing a regenerated clock signal in synchronism with a center of a time duration 1/FD of said regenerated data signal.

Claim 6

A DIDON demodulator according to claim 3 further including a synchronization extraction circuit for utilizing the configuration signals and the second signal in order to identify the leading edge of line-synchronization signals of said DIDON television video signal, said synchronization extraction circuit being provided with a counter for producing a regenerated line-synchronization signal and a data-validation window signal from an instant of identification of the leading edge of a line-synchronization signal.

Claim 7

A DIDON demodulator according to claim 3, wherein said data-regenerating circuit includes: signal input means for receiving the configuration signals; input means for receiving from the electronic switch the signal at the frequency n×FB and no signal at all respectively when the first signal corresponds to a probable configuration or to an improbable configuration, said data regenerating means providing a regenerated data signal having a time-duration 1/FD when the configuration is probable and presenting four different values respectively corresponding to whether the configuration is a "+" transition, a "-" transition, a low stable-state or a high stable-state, said data regeneration means also providing a regenerated clock signal in synchronism with a center of a time duration 1/FD of said regenerated data signal, said DIDON demodulator comprising a synchronization extraction circuit for utilizing the configuration signals and the second signal in order to identify the leading edge of line-synchronization signals of said DIDON television video signal, said synchronization extraction circuit being provided with a counter for producing a regenerated line-synchronization signal and a data-validation window signal from an instant of identification of the leading edge of a line-synchronization signal.

Claim 8

A DIDON demodulator according to claim 6, further including validation means for producing a data-validation signal, said validation means having means for identifying a synchronization burst which appears at a start of a DIDON data signal by identifying a predetermined number of alternate 0s and 1s in the regenerated data signal during the data-validation window signal.